Always-On Buffer Fault Detection for IC Supply Glitch Attacks
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Solution Overview
Problem
Conventional fault detection systems in integrated circuits (ICs) are area and power inefficient due to the use of analog components, limiting their effectiveness against various fault injection attacks, and are not operational during the booting process, leaving the IC vulnerable.
Innovation Solution
An IC design incorporating a digital always-on buffer and logic circuit that detects fault injection attacks by monitoring a secondary global supply voltage, allowing for broader attack detection and reduced area and power consumption, with integrated recovery mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog components (voltage reference generators, delay lines, comparators) are used in the fault detector, then the fault detection capability is improved, but the area occupied by the fault detector increases significantly
Solution Approach 1:
The patent replaces analog components (voltage reference generators, delay lines, comparators) with digital components (always-on buffer, logic circuit). This substitution fundamentally changes the detection mechanism from analog voltage comparison to digital logic state monitoring, thereby reducing the area occupied by the fault detector while maintaining fault detection capability.
Solution Approach 2:
The patent changes the operating parameters of the fault detector by using a digital always-on buffer that operates at reduced supply voltage (second global supply voltage less than first global supply voltage). This parameter change allows the buffer to remain operational during booting and detect faults across different voltage conditions without requiring large analog components.
2Reliability
If analog components with continuous switching are used in the fault detector, then the fault detection function is maintained, but the dynamic power consumption increases significantly
Solution Approach 1:
The patent replaces analog components with continuous switching (which consume dynamic power) with digital components that can operate in static states. The always-on buffer and logic circuit detect faults by monitoring logic states rather than continuously switching analog signals, thereby significantly reducing dynamic power consumption while maintaining the fault detection function.
3Ease of operation
If the fault detector is not enabled during the booting process, then the IC can be powered up, but the IC is unprotected during a portion of the booting process
Solution Approach 1:
The patent implements an always-on buffer that is enabled before the main IC operation begins, specifically during the booting process. This preliminary action ensures that the fault detection mechanism is already active and monitoring when the IC is most vulnerable, without requiring additional power management complexity that would hinder the power-up process.
Solution Approach 2:
The patent uses a second global supply voltage that is less than the first global supply voltage and is controlled based on power line characteristics. This parameter change allows the always-on buffer to operate at reduced voltage during booting, enabling fault detection functionality during the booting process without preventing the IC from powering up successfully.
4Device complexity
If a fault detector is designed to detect exclusively power glitching attacks, then the detection logic is simplified, but the IC remains vulnerable to other types of fault injection attacks
Solution Approach 1:
The patent designs the fault detector with universal applicability by using an always-on buffer and logic circuit that can detect multiple types of fault injection attacks (power glitching, electromagnetic attacks, and others) rather than being specialized for only one attack type. The digital logic structure inherently monitors for various fault conditions, providing multi-functional protection without significantly increasing complexity.
Data Source
AI summary
An integrated circuit (IC) that includes an always-on buffer and a power line is provided. The power line is routed on the IC such that a first end of the power line is at a first global supply voltage and a second end of the power line is at a second global supply voltage that is less than the first global supply voltage. The always-on buffer receives an input bit and the second global supply voltage and generates an output bit that has a same logic state as that of the input bit. During a fault injection attack, the second global supply voltage is altered such that the logic state of the output bit toggles while the logic state of the input bit remains same. Based on the toggling of the logic state of the output bit, the fault injection attack on the IC is detected.


