Interconnect Chip for AMBA to PCIe IOAPIC Interrupt Translation
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Solution Overview
Problem
AMBA® based peripheral IO devices are incompatible with PCIe based host systems due to differences in interrupt handling protocols, specifically the lack of support for IOAPIC style interrupts, which prevents direct interaction between AMBA® compliant IO devices and PCIe compliant computing systems.
Innovation Solution
An interconnect chip is introduced that communicates with AMBA® compliant IO devices via the AMBA® bus and with the PCIe compliant host system via PCIe links, enabling the receipt of commands, DMA operations, and IOAPIC interrupts that adhere to PCIe ordering rules, ensuring data integrity and compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an interconnect chip is introduced to enable communication between AMBA and PCIe systems, then compatibility and communication capability are improved, but device complexity increases
Solution Approach 1:
An interconnect chip is introduced as an intermediary device between AMBA-based IO devices and PCIe-based host systems. This chip contains both an AMBA interface and a PCIe interface, translating commands, data, and interrupts between the two different bus protocols. The intermediary handles protocol conversion, enabling compatibility without requiring changes to the existing AMBA or PCIe components.
2Reliability
If PCIe ordering rules are enforced to ensure correct interrupt handling, then reliability of producer-consumer model is improved, but communication efficiency deteriorates
Solution Approach 1:
The interconnect chip performs preliminary actions by pre-processing and ordering commands before they reach the AMBA IO device. It ensures that all PCIe ordering rules are satisfied in advance by properly sequencing read commands and interrupt notifications. This preliminary ordering prevents violations of the producer-consumer model while maintaining efficient communication through optimized command batching and parallel processing where possible.
Data Source
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AI summary
One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.