Ambient Light Sensor Delta-Sigma ADC Switch Network for Low-Noise Gain
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Solution Overview
Problem
Existing delta-sigma analogue to digital converter techniques face challenges in achieving high gain and low noise operations, particularly in measuring low light levels, due to issues like clock feedthrough and switch-associated errors, which affect the accuracy and sensitivity of ambient light sensing in electronic devices.
Innovation Solution
A sensor circuit with a delta-sigma analogue to digital converter incorporating a switch network configuration that allows for increased gain and reduced noise by sampling either the sum or difference of common mode and reference voltages, using a two-phase clock operation to minimize switch errors and enable decimation for improved signal-to-noise ratio, and featuring a second-order converter with additional integrator stages for enhanced noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional delta-sigma ADC techniques are used, then the circuit can perform basic light sensing, but the gain is limited and noise is high, preventing measurement of very low light levels
Solution Approach 1:
The patent divides the conversion process into multiple discrete phases (first clock phase for charging, second clock phase for transfer) using a multi-phase clocking scheme. This segmentation allows separate optimization of charging accuracy and transfer precision, reducing noise while maintaining gain.
Solution Approach 2:
The patent employs periodic clocking with multiple phases to systematically charge and transfer voltages through the switch network. This periodic action with controlled timing reduces random noise and enables coherent integration of signal over multiple cycles, improving measurement precision for low light levels.
2Measurement precision
If gain is increased to improve sensitivity, then low light levels can be detected, but noise also increases, degrading signal quality
Solution Approach 1:
The patent performs preliminary charging of capacitors to precise voltage levels (Vcm+Vref or Vcm-Vref) before the measurement phase. This preliminary action establishes accurate reference states that enable high gain operation without proportionally increasing noise, as the charging phase is optimized for precision rather than speed.
Solution Approach 2:
The patent introduces common mode voltage (Vcm) as an intermediary that mediates between the reference voltage and the integrator operation. This intermediary allows the circuit to achieve high gain through differential voltage swings while the common mode component remains stable and noise-free, decoupling gain from noise amplification.
3Device complexity
If switch network operation is simplified, then circuit complexity is reduced, but clock feedthrough and charge injection errors increase, affecting accuracy
Solution Approach 1:
The patent segments the switch network operation into distinct non-overlapping phases controlled by multi-phase clocks. Each phase handles a specific function (charging from Vcm+Vref, charging from Vcm-Vref, or transfer to integrator), which simplifies the switching logic while minimizing clock feedthrough and charge injection by ensuring clean transitions between phases.
Solution Approach 2:
The patent implements preliminary anti-action by using correlated double sampling and differential switching where the effects of charge injection and clock feedthrough are generated symmetrically in opposite phases and then subtracted during integration. This preliminary anti-action cancels out the errors before they affect the measurement, maintaining accuracy without complex compensation circuits.
Data Source
AI summary
An ambient light sensor is provided that includes a sensor input having a delta-sigma analogue to digital converter. The delta-sigma analogue to digital converter includes a switched capacitor, a common mode voltage source, a reference voltage source, and a switch network. In a first clock phase, the switch network connects the switched capacitor to charge it to either a sum or difference voltage. In a second clock phase, the switch network connects the switched capacitor to transfer charge into a summing junction. A controller controls the switch network in response to a comparator output to connect the switched capacitor to either the common mode voltage or the reference voltage while in the first clock phase.