Ambipolar Field-Effect Devices with Engineered Work-Functions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As CMOS devices approach sub-10 nm scales, it becomes challenging to fabricate transistors with sufficient ION/IOFF current ratios for effective performance in logic circuits, with conventional incremental changes reaching fundamental limits due to parasitic and quantum effects.
Innovation Solution
The use of ambipolar field-effect devices with engineered work-functions, specifically Schottky-Barrier FinFETs having multiple gates, allows for independent adjustment of carrier densities and Schottky barrier heights, enabling operation as both n-channel and p-channel MOSFETs, and reducing transistor count and power-delay products.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CMOS devices are downscaled to sub-10 nm scale, then device density and integration are improved, but the ION/IOFF current ratio deteriorates due to parasitic and quantum effects
Solution Approach 1:
The patent changes the fundamental operating parameters of the device by introducing ambipolar field-effect devices with engineered work-functions. By adjusting the work-function of the gate electrode and contact materials, the device can operate in both n-channel and p-channel modes, enabling sufficient ION/IOFF current ratios even at sub-10 nm scale where conventional CMOS fails due to quantum tunneling and parasitic effects
Solution Approach 2:
The patent employs composite material structures including Schottky-Barrier FinFETs with multiple gates having different work-functions. The combination of semiconductor layer, gate dielectric, and metal gates with engineered work-function differences creates a composite structure that enables ambipolar operation and maintains performance at ultra-scaled dimensions
2Ease of manufacture
If conventional CMOS devices use incremental structural changes, then fabrication compatibility is maintained, but performance improvement is limited by fundamental physical effects
Solution Approach 1:
Rather than making incremental structural changes, the patent fundamentally changes the device operating mode from unipolar to ambipolar by engineering work-functions. This parameter change enables performance breakthroughs while remaining compatible with existing CMOS fabrication processes, as the same basic device structures are used but with modified material properties
3Loss of energy
If ambipolar field-effect devices with engineered work-functions are used, then transistor count and power consumption are reduced, but device structure complexity increases
Solution Approach 1:
The ambipolar field-effect device with engineered work-functions serves multiple functions: it can operate as both n-channel and p-channel MOSFET, enabling logic circuit implementation with fewer transistors. The same device structure performs the work of what would traditionally require separate nMOS and pMOS devices, reducing overall circuit complexity and power consumption despite the sophisticated work-function engineering required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables ultra-compact logic circuits with reduced transistor counts and power consumption, achieving improved performance and scalability down to 5 nm gate lengths, with a 50% reduction in area and up to 10 times lower power consumption compared to conventional CMOS logic circuits.
Implementation Method 1
the coupling of gate electrodes to the surface of the semiconductor layer may be via electro-static field action
Implementation Method 2
the coupling of contacts to the ends of the semiconductor layer may be via quantum mechanical tunneling though the Schottky Barrier
Data Source
AI summary
Devices, circuits, and methods for fabricating circuits. A device having ambipolar characteristics includes a semiconductor layer and multiple gates, a source contact, and a drain contact coupled to the semiconductor layer. One channel may have elections as the majority charge carrier and may be formed proximate to one of the gates. Another channel may have holes as the majority charge carrier and be formed proximate another gate. Each of the channels is generally parallel to the other and couples the source contact to the drain contact. The device may be optimized by adjusting the work-functions in one or more of source and drain contacts or gates to compensate for differences in the effective masses of the majority carriers in each of the channels. The ambipolar nature of the devices allows logic circuits to be fabricated using one or two of the devices.