Ambipolar Transistor Neuromorphic Device for Multi-Layer Neural Network Computation
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Solution Overview
Problem
Existing neuromorphic hardware struggles with efficient multi-layer artificial neural network computations due to high power consumption and large area requirements, primarily because of the need for multiple arrays and extensive driving circuits like ADCs.
Innovation Solution
A neuromorphic device utilizing an ambipolar transistor-based non-volatile memory array, which can perform two-layer operations within a single array by storing two weights in one synaptic device, thereby reducing the number of ADCs and driving circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing neuromorphic hardware uses multiple arrays for multi-layer operations, then computation capability is improved, but chip area and power consumption increase
Solution Approach 1:
The patent merges multiple computation layers into a single neuromorphic array by utilizing the temporal multiplexing capability of ambipolar transistors. Different layers are computed sequentially within the same array structure, eliminating the need for multiple physical arrays and reducing chip area while maintaining multi-layer computation capability.
Solution Approach 2:
The ambipolar transistor-based synaptic device is designed to perform multiple functions: it can store weights for different layers, perform analog multiplication for multiple layers, and support both training and inference operations within a single device structure, thereby reducing the overall hardware footprint.
2Productivity
If existing neuromorphic hardware uses multiple arrays for multi-layer operations, then computation capability is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple layer computations into a single array operation sequence. By performing computations for different layers in temporal sequence within the same hardware resources, the patent eliminates redundant power consumption associated with multiple separate arrays and their respective support circuits.
Solution Approach 2:
The patent employs periodic switching between different layer computations within the same array. The ambipolar transistors are alternately activated for different layers in a time-multiplexed manner, allowing the system to maintain multi-layer computation capability while keeping power consumption comparable to a single layer operation.
3Measurement precision
If ADC circuits are added for analog parallel computations, then computation precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the analog-to-digital conversion function from the traditional neuromorphic architecture by utilizing the inherent switching characteristics of ambipolar transistors. The transistors naturally perform threshold-based activation that effectively converts analog synaptic currents into digital-like output signals, eliminating the need for separate ADC circuits.
Solution Approach 2:
The ambipolar transistor structure provides self-conversion capability where the device's own switching characteristics enable the transition from analog weight storage to digital-like computation output. This self-service mechanism eliminates external ADC requirements while maintaining computation precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the chip area and power consumption by half, enabling more efficient artificial neural network operations while maintaining high integration and performance.
Implementation Method 1
a non-volatile memory array including an ambipolar transistor disposed in a region where the bit lines and the word lines intersect. The non-volatile memory array may perform two-layer operation by implanting different weights in two current regions present in the ambipolar transistor. The non-volatile memory array may alternately applies specific voltages of first and second polarities to word lines and bit lines connected to specific synaptic devices among the plurality of bit lines and the plurality of word lines to perform weight implantation for multi-layer learning.
Data Source
AI summary
A neuromorphic device includes: a plurality of bit lines; a plurality of word lines; and a non-volatile memory array including an ambipolar transistor disposed in a region where the bit lines and the word lines intersect. The non-volatile memory array uses the ambipolar transistor as a synaptic device. The non-volatile memory array performs two-layer operation by implanting different weights in two current regions present in the ambipolar transistor. The non-volatile memory array alternately applies specific voltages of first and second polarities to word lines and bit lines connected to specific synaptic devices among the plurality of bit lines and the plurality of word lines to perform weight implantation for multi-layer learning.