AMOLED Sub-Pixel Circuit Layout to Reduce Parasitic Capacitance
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Solution Overview
Problem
As the resolution of AMOLED display panels increases, the close proximity of the gate electrode of the driving transistor to the data line patterns leads to parasitic capacitance, causing abnormal brightness in some areas and affecting display quality.
Innovation Solution
The display panel includes a substrate with a sub-pixel driving circuit film layer, gate line layer, data line layer, and conductive connection portion layer, where the gate line pattern and data line pattern intersect, and the conductive connection portions are positioned to prevent overlap with the gate line pattern, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the gate electrode is positioned close to the data line pattern to save layout space, then the area utilization is improved, but parasitic capacitance increases causing abnormal brightness
Solution Approach 1:
An insulating layer is introduced as an intermediary between the gate electrode and the data line pattern. This insulating layer physically separates the two conductive elements while allowing them to remain in close proximity, thereby reducing parasitic capacitance without sacrificing layout space efficiency.
Solution Approach 2:
The solution moves from a two-dimensional planar separation to a three-dimensional layered structure. By stacking the gate electrode, insulating layer, and data line pattern in different vertical layers, the design achieves both close horizontal spacing (for area efficiency) and vertical separation (for parasitic capacitance reduction).
Data Source
AI summary
The present disclosure provides a display panel and a method of manufacturing the same and a display device. In a sub-pixel driving circuit of the display panel, a gate electrode of a driving transistor is coupled to a second electrode of a second transistor through a fourth conductive connection portion, and a second electrode plate of a storage capacitor is coupled to a second electrode of a first transistor through a third conductive connection portion, a gate electrode of the first transistor and a gate electrode of the second transistor are respectively coupled to a gate line pattern in the corresponding sub-pixel area; orthographic projection of the gate line pattern on the substrate does not overlap orthographic projection of the third conductive connecting portion on the substrate, and/or does not overlap orthographic projection of the fourth conductive connection portion on the substrate.