AMOLED DAC Circuit With Low-Voltage Decoding and Amplification
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Solution Overview
Problem
Current digital-to-analog conversion circuits for large-sized AMOLED source drivers face challenges in maintaining high performance while minimizing footprint, with existing DAC structures either consuming high power or limited in precision due to large area requirements and high voltage needs.
Innovation Solution
A digital-to-analog conversion circuit comprising a voltage dividing sub-circuit, decoding sub-circuit, and amplification sub-circuit, where the decoding sub-circuit selects one of multiple voltage dividing signal terminals based on a digital signal, and the amplification sub-circuit amplifies the signal with an amplification coefficient greater than or equal to 2, reducing the voltage range and allowing for smaller switches and lower power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the DAC structure uses high precision decoding, then the conversion precision is improved, but the area occupied by the decoding circuit increases
Solution Approach 1:
The patent divides the decoding process into multiple stages using a tree-structured switch network. Instead of directly selecting from M voltage dividing terminals, the decoding is segmented into multiple levels where each level handles a portion of the selection, reducing the complexity and area of individual switching elements while maintaining overall precision.
Solution Approach 2:
The patent transforms the direct M-way selection problem into a multi-level hierarchical selection process. By organizing switches in a tree structure with multiple levels, the patent converts a single-dimension large-scale selection into a multi-dimension progressive selection, reducing the area requirement at each level.
2Power
If the voltage dividing signal uses full range voltage, then the output voltage range is improved, but the power consumption increases
Solution Approach 1:
The patent changes the voltage parameter by using voltage dividing terminals that output voltages less than or equal to 1/2 of the maximum load voltage. Combined with an amplification coefficient N≥2, this parameter transformation allows the circuit to achieve full output voltage range while operating at lower voltages during conversion, thereby reducing power consumption.
3Power
If the switch network uses large voltage rating, then the voltage handling capability is improved, but the switch area increases
Solution Approach 1:
The patent segments the voltage handling requirement across multiple levels of the switch network. Each switch in the tree structure only needs to handle a portion of the total voltage range, allowing the use of smaller area switches while collectively achieving the required voltage handling capability through the hierarchical structure.
Solution Approach 2:
The patent transforms the voltage parameter requirement by using voltage dividing terminals with voltages ≤1/2 of maximum load voltage. This parameter change allows switches to operate at lower voltage ratings, significantly reducing switch area while the amplification stage restores the full output voltage range.
4Area of stationary object
If the DAC structure is optimized for small area, then the footprint is reduced, but the precision deteriorates
Solution Approach 1:
The patent segments the precision requirement across multiple decoding levels. Each level contributes to the overall precision through its switching action, and the cumulative effect of multiple precise level selections achieves high overall precision with smaller individual components, reducing total area.
Solution Approach 2:
The patent uses a multi-level hierarchical decoding structure that transforms a single-dimension precision requirement into a multi-dimension progressive precision achievement. Each level adds a portion of the precision requirement, allowing the system to achieve high overall precision while using smaller area elements at each level.
Data Source
AI summary
Digital-to-analog conversion circuit, digital-to-analog conversion method, display apparatus are disclosed. Digital-to-analog conversion circuit may comprise: voltage dividing sub-circuit comprising M voltage dividing signal terminals; decoding sub-circuit comprising M input and output terminals, M input terminals electrically coupled to first to Mth voltage dividing signal terminals of voltage dividing sub-circuit respectively, decoding sub-circuit configured to receive digital signal and select one of M input terminals to be electrically connected with output terminal according to digital signal; amplification sub-circuit comprising input and output terminals, input terminal of amplification sub-circuit electrically coupled to output terminal of decoding sub-circuit, amplification sub-circuit configured to amplify signal at its input terminal, output analog gray-scale voltage at output terminal, voltage dividing signal at voltage dividing signal terminal is less than or equal to ½ of maximum load voltage at output terminal of digital-to-analog conversion circuit, amplification sub-circuit has amplification coefficient N greater than or equal to 2.