AMOLED Display Panel Insulating Layer Layout for Uniform IGZO TFT Etching
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Solution Overview
Problem
Large-sized AMOLED displays face issues with non-uniformity and high parasitic capacitance due to non-uniform processes, leading to degradation in display performance, particularly in top gate IGZO TFT devices.
Innovation Solution
The implementation of an increased second insulating layer over-etching process to enhance the uniformity of the oxide conductor layer and improve electrical stability, which involves a substrate with a first insulating layer having regions of different thicknesses, allowing for better contact and reduced electrical resistance between metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a top gate structure is used to reduce parasitic capacitance, then parasitic capacitance is reduced, but non-uniformity in etching process occurs
Solution Approach 1:
The first insulating layer is designed with different thicknesses in different regions: a first thickness in the first region and a second thickness (less than the first) in the second region. This local variation in thickness enables uniform etching depth across different areas, allowing the etching process to reach the oxide semiconductor layer uniformly while maintaining the top gate structure's parasitic capacitance reduction benefit.
Solution Approach 2:
The first insulating layer with non-uniform thickness is formed in advance before the etching process. This preliminary structuring ensures that when etching is performed, the varying thickness compensates for the different distances to the oxide semiconductor layer, achieving uniform etching results without requiring adjustment during the etching process itself.
2Ease of manufacture
If the first insulating layer has uniform thickness, then manufacturing is simpler, but electrical contact uniformity deteriorates
Solution Approach 1:
The first insulating layer is designed with different thicknesses in different regions: a first thickness in the first region and a second thickness (less than the first) in the second region. This local variation in thickness enables uniform etching depth across different areas, allowing the etching process to reach the oxide semiconductor layer uniformly while maintaining the top gate structure's parasitic capacitance reduction benefit.
3Reliability
If etching depth is increased to improve contact, then electrical resistance is reduced, but light-shielding characteristics are compromised
Solution Approach 1:
The first insulating layer is designed with different thicknesses in different regions: a first thickness in the first region and a second thickness (less than the first) in the second region. This local variation in thickness enables uniform etching depth across different areas, allowing the etching process to reach the oxide semiconductor layer uniformly while maintaining the top gate structure's parasitic capacitance reduction benefit.
Solution Approach 2:
The first insulating layer with non-uniform thickness is formed in advance before the etching process. This preliminary structuring ensures that when etching is performed, the varying thickness compensates for the different distances to the oxide semiconductor layer, achieving uniform etching results without requiring adjustment during the etching process itself.
Data Source
AI summary
A display panel includes a substrate, a first metal layer, and a first insulating layer, an oxide semiconductor layer, a second insulating layer, a second metal layer, a third insulating layer, and a third metal layer stacked on each other sequentially. The first insulating layer includes a first region and a second region adjacent to the first region, and a thickness of the second region is less than a thickness of the first region. A projection of at least a portion of the oxide semiconductor layer projected on the substrate overlaps with a projection of the first metal layer projected on the substrate. The third metal layer is connected to the first metal layer through a third via hole, and the third via hole is extended through the first insulating layer and the third insulating layer.