AMOLED Array Substrate Power Bus Layout to Cut Parasitic Capacitance
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Solution Overview
Problem
Existing array substrates for AMOLED displays face issues due to overlapping power buses and selector switches, which result in parasitic capacitance and affect the normal operation of both components.
Innovation Solution
The array substrate design includes a first power bus and a second power bus in the peripheral region that do not overlap with the selector switches, reducing parasitic capacitance and allowing both the power bus and selector switch to function normally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the power bus is arranged in the peripheral region overlapping with the selector switch, then the device complexity is reduced, but parasitic capacitance increases affecting normal operation
Solution Approach 1:
The power bus is segmented into multiple sections: a first power bus in the peripheral region, a second power bus in the display region, and multiple connecting portions that bridge them. This segmentation allows the power bus to bypass the selector switch area, avoiding parasitic capacitance while maintaining structural organization.
Solution Approach 2:
The power bus transitions from a two-dimensional planar arrangement to a three-dimensional path by extending through different spatial dimensions. The connecting portions route the power bus through regions above and below the selector switch plane, effectively moving the power transmission path to another dimension to avoid interference.
2Object-generated harmful factors
If the power bus and selector switch are separated to reduce parasitic capacitance, then parasitic capacitance is reduced, but the manufacturing process becomes more complex
Solution Approach 1:
Multiple structures (first power bus, second power bus, and connecting portions) are merged into the same manufacturing layer. This consolidation allows all power bus components to be fabricated simultaneously using a single set of photolithography and deposition processes, eliminating the need for additional manufacturing steps despite the complex routing path.
3Object-generated harmful factors
If the power bus routes through the peripheral region, then parasitic capacitance is reduced, but the power signal transmission path becomes longer
Solution Approach 1:
The power bus configuration is optimized to dynamically balance path length and interference avoidance. The connecting portions are positioned and sized to provide the shortest possible route that still maintains adequate separation from the selector switch, creating an optimized transmission path that minimizes both length and parasitic capacitance.
Data Source
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AI summary
The present disclosure provides an array substrate and a display device. The array substrate includes: a base substrate, a plurality of sub-pixels, a plurality of data lines, a plurality of first power lines and a plurality of data line leads; and the array substrate further includes: a plurality of selector switches, located in a peripheral region and arranged at intervals, the plurality of selector switches being located at a side of the plurality of data line leads away from a display region; a plurality of data signal input lines, located in the peripheral region and located at a side of the plurality of selector switches away from the display region, each of at least a part of the plurality of selector switches being connected to one of the plurality of data signal input lines; a first power bus, located in the peripheral region, and located at a side of the plurality of selector switches away from the display region; and a plurality of connecting portions, connected to the first power bus and the plurality of first power lines, the plurality of connecting portions extending towards the display region along regions between the plurality of selector switches. The present disclosure may implement effective transmission of power signals.