AMOLED Scan Driver Clock Grouping for Brightness Uniformity
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Solution Overview
Problem
Existing scan driver circuits in AMOLED displays suffer from poor brightness uniformity due to large signal line loads and uneven signal transition times, leading to display defects.
Innovation Solution
The proposed scan driver circuit includes multiple clock signal lines divided into groups, with shift registers connected in a specific configuration to reduce signal line loads and optimize signal transitions, using transistors and capacitors to control node voltages and improve output signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple cascaded shift registers are used in the scan driver circuit, then the display device can achieve basic scanning function, but the signal line load increases and signal transition times become uneven, leading to poor brightness uniformity
Solution Approach 1:
The clock signal lines are divided into multiple groups (first clock signal line group and second clock signal line group), with each group containing multiple clock signal lines. This segmentation distributes the signal line load across multiple parallel paths, preventing any single line from becoming overloaded, which improves signal transition uniformity and brightness uniformity while maintaining the basic scanning function
Solution Approach 2:
The patent introduces multiple dimensions of clock signal organization by creating groups of clock signal lines and assigning different signal terminals to different groups. This multi-dimensional arrangement balances the load distribution across the circuit, reducing signal transition time differences and improving brightness uniformity without increasing overall device complexity
2Reliability
If signal line load is reduced to improve brightness uniformity, then display quality improves, but the circuit configuration becomes more complex
Solution Approach 1:
Multiple clock signal lines within each group serve universal functions by connecting to different signal terminals (first, second, and third signal terminals) of cascaded shift registers. This multi-functional arrangement distributes the signal line load across multiple lines, reducing the burden on any single line and improving brightness uniformity, while the modular group structure keeps the circuit configuration manageable
Data Source
AI summary
The present disclosure relates to a scan driver circuit including clock signal lines and cascaded shift registers. The shift registers include an input sub-circuit, a first control sub-circuit, a second control sub-circuit and an output sub-circuit. The input sub-circuit is connected to a starting signal terminal, a first node and a first signal terminal. The first control sub-circuit is connected to the first signal terminal, the first node and a second node. The second control sub-circuit is connected to the first node, the second node, a second voltage terminal and a third signal terminal. The output sub-circuit is connected to the first node, the second node, an output terminal, a second signal terminal and the second voltage terminal. The second signal terminal and the third signal terminal of the same shift register are connected to different clock signal lines.