AMOLED Array Substrate Layout for Uniform Row Compensation
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Solution Overview
Problem
Existing pixel driving circuits in AMOLED displays experience inconsistent compensation durations due to differing parasitic capacitances between odd and even numbered rows, leading to uneven brightness and poor display quality.
Innovation Solution
The array substrate design includes alternately arranged odd and even numbered row circuit groups with conductive patterns in different layers, reducing overlapping areas and parasitic capacitances to equalize compensation durations across rows, ensuring consistent brightness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional pixel driving circuits are used with standard conductive pattern layouts, then the circuit structure is simple and easy to manufacture, but parasitic capacitances differ between odd and even rows causing inconsistent compensation durations and uneven brightness
Solution Approach 1:
The patent applies local quality by making the conductive connection pattern continuous specifically in the second semiconductor layer for odd-numbered row circuit groups, while even-numbered rows use conventional patterns. This localized modification equalizes parasitic capacitances between odd and even rows without requiring changes to the entire display structure, thereby achieving brightness uniformity while maintaining manufacturing feasibility.
Solution Approach 2:
The patent introduces asymmetry in the conductive pattern design where odd-numbered row circuit groups have a continuous conductive connection pattern in the second semiconductor layer, while even-numbered rows follow the conventional discontinuous pattern. This asymmetric design compensates for the inherent parasitic capacitance differences between odd and even rows, enabling consistent compensation durations and uniform brightness across all rows.
2Duration of action of moving object
If the conductive connection pattern is made continuous in the second semiconductor layer for odd rows, then parasitic capacitances are equalized and compensation durations become consistent, but the device structure becomes more complex
Solution Approach 1:
The patent resolves the contradiction by utilizing the vertical dimension (layer structure) to solve a horizontal problem (compensation duration consistency). By making the conductive connection pattern continuous specifically in the second semiconductor layer for odd-numbered rows, the patent equalizes parasitic capacitances without affecting other layers excessively, thereby achieving consistent compensation durations while limiting the increase in overall device complexity.
3Manufacturing precision
If different conductive pattern overlapping areas are used for odd and even row circuit groups, then parasitic capacitances are balanced, but the manufacturing process becomes more difficult
Solution Approach 1:
The patent applies segmentation by dividing the display into odd-numbered and even-numbered row circuit groups with different conductive pattern configurations. The continuous conductive connection pattern is implemented only in the second semiconductor layer for odd rows, while even rows use the conventional pattern. This segmented approach allows precise control of parasitic capacitances for each row type while maintaining compatibility with existing manufacturing processes.
Data Source
AI summary
An array substrate includes a substrate, pixel driving circuits and conductive patterns. In each pixel driving circuit, a first electrode region of a driving transistor, a second electrode region of a data writing transistor and a second electrode region of a first light-emitting control transistor are connected through a conductive connection pattern. The pixel driving circuits are configured as odd-numbered row circuit groups and even-numbered row circuit groups. The odd-numbered row circuit groups and the even-numbered row circuit groups each include pixel driving circuits. An overlapping area of orthographic projections, on the substrate, of a conductive connection pattern and a conductive pattern in at least one pixel driving circuit in an odd-numbered row circuit group is less than an overlapping area of orthographic projections, on the substrate, of a conductive connection pattern and a conductive pattern in at least one pixel driving circuit in an even-numbered row circuit group.