AMOLED Top-Gate TFT Manufacturing via Shared Photomask Layers
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Solution Overview
Problem
The manufacturing of top-gate thin film transistors for AMOLED display panels is hindered by a complex structure and increased number of film layers, leading to longer manufacturing times and higher costs.
Innovation Solution
A method involving the sequential deposition and etching of layers on a substrate, including a transparent electrode, metal layers, buffer, oxide, and insulating layers, with shared photomasks to form light-shielding, source, gate, and drain structures, and subsequent pixel defining, light-emitting, and cathode layers, optimizing the process to reduce complexity and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If top-gate thin film transistor structure is adopted to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing time and cost increase due to complex structure and more film layers
Solution Approach 1:
The patent merges the formation of the buffer layer and insulating layer into a single photomask process step. By depositing both layers sequentially and patterning them simultaneously using one photomask, the manufacturing process reduces the number of separate photomask steps required, thereby decreasing manufacturing time and complexity while maintaining the top-gate TFT structure that provides low parasitic capacitance
2Reliability
If top-gate thin film transistor structure is adopted to reduce parasitic capacitance, then parasitic capacitance is reduced, but manufacturing cost increases due to complex structure and more film layers
Solution Approach 1:
The patent combines multiple layer formations into fewer process steps. Specifically, the buffer layer and insulating layer are formed in one photomask operation, and the source, gate, and drain are formed in another photomask operation. This merging of steps reduces the total number of photomasks and process operations required, thereby lowering manufacturing cost while preserving the low parasitic capacitance benefits of the top-gate structure
3Manufacturing precision
If multiple photomasks are used to form buffer layer and insulating layer separately, then layer precision is maintained, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the photomask steps for forming the buffer layer and insulating layer into a single photomask process. The photomask is designed to define patterns for both layers simultaneously, allowing them to be patterned in one exposure and development cycle. This approach maintains alignment precision between the layers while significantly reducing the overall process complexity by eliminating separate photomask fabrication, alignment, and exposure steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method streamlines the manufacturing process, saving time and cost by forming multiple layers simultaneously and reducing the need for multiple photomasks, thereby enhancing efficiency in producing display panels.
Implementation Method 1
depositing a transparent electrode layer and a first metal layer on the substrate
Implementation Method 2
depositing a second metal layer on the insulating layer
Data Source
AI summary
A method of manufacturing a display panel and the display panel are provided. The method of manufacturing the display panel includes providing a substrate; depositing a transparent electrode layer and a first metal layer on the substrate, and etching the transparent electrode layer and the first metal layer to form a light-shielding layer and an anode; forming a buffer layer, an oxide layer, and an insulating layer on the light-shielding layer in sequentially, and the buffer layer and the insulating layer are formed by a same photomask; depositing a second metal layer on the insulating layer and etching the second metal layer to form a source, a gate, and a drain; and forming a pixel defining layer, a light-emitting layer, and a cathode layer on the second metal layer in sequentially.