Amorphized Silicon IPD Isolation via Inert Implant
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Solution Overview
Problem
Conventional integrated passive devices (IPDs) on silicon substrates suffer from parasitic coupling due to charge accumulation at the substrate-insulating layer interface, leading to increased RF losses and decreased linearity, which is exacerbated by the low resistivity of bulk silicon substrates.
Innovation Solution
An inert implant is used to create a disordered or amorphized silicon layer at the surface of a high resistivity silicon wafer, increasing carrier trap density and preventing the formation of a parasitic conduction layer, thereby enhancing resistivity and reducing RF losses and improving linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If an insulating layer is used to isolate the substrate from signal-carrying conductive layers, then RF losses through the substrate are reduced, but charge accumulation occurs at the interface forming a parasitic conduction layer that increases power loss and decreases linearity
Solution Approach 1:
A preliminary amorphization step is performed on the silicon substrate surface before depositing the insulating layer. This creates a high-resistivity amorphous silicon layer that prevents charge accumulation when the insulating layer is subsequently added, thereby avoiding PCL formation while maintaining RF isolation.
Solution Approach 2:
An amorphous silicon layer is introduced as an intermediary between the crystalline silicon substrate and the insulating layer. This intermediate layer acts as a charge trap that prevents charge accumulation at the insulator-silicon interface, eliminating the parasitic conduction layer while maintaining electrical isolation.
2Reliability
If a fully insulating substrate such as quartz or sapphire is used, then parasitic coupling and charge accumulation are avoided, but manufacturing cost increases significantly and integration into silicon manufacturing becomes difficult
Solution Approach 1:
The electrical parameters of the silicon substrate surface are changed by amorphizing the top layer, transforming it from a low-resistivity crystalline state to a high-resistivity amorphous state. This allows the substrate to achieve isolation properties similar to fully insulating substrates while maintaining compatibility with standard silicon manufacturing processes.
3Reliability
If SOI wafers with a trap-rich layer are used to mitigate the parasitic conduction layer, then PCL formation is reduced, but manufacturing cost increases significantly
Solution Approach 1:
Instead of using expensive SOI wafers, the invention creates a temporary amorphous layer on standard silicon substrates that serves the same function of preventing PCL formation. This approach achieves the desired reliability improvement using inexpensive, readily available bulk silicon substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces RF losses and improves linearity and isolation in IPDs by preventing the formation of a parasitic conduction layer, allowing the substrate to perform closer to ideal high resistivity silicon.
Implementation Method 1
An inert implant is used to create a disordered or amorphized silicon layer at the surface of a high resistivity silicon wafer
Implementation Method 2
increasing carrier trap density and preventing the formation of a parasitic conduction layer, thereby enhancing resistivity
Data Source
AI summary
Disclosed is a structure for improved electrical signal isolation in a semiconductor substrate between integrated passive devices (IPDs) and an associated method for the structure's fabrication. The structure includes an amorphized region in the semiconductor substrate, a dielectric layer formed over the amorphized region, and IPDs formed over the dielectric layer. The amorphized region is not recrystallized and may be formed by utilizing an inert implant that does not charge-dope the amorphized region, while forming a plurality of charge carrier traps at an interface between the amorphized region and the dielectric layer to prevent a parasitic conduction layer from forming at the interface. The inert implant may include one of Argon, Xenon and Germanium. In many implementations, the structure does not include an active device.