Amorphized Subfins Using Backside Implantation for Soft Error Reduction
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Solution Overview
Problem
As integrated circuits scale downward in size, parasitic effects from densely packed transistors increase, leading to parasitic current and higher soft error rates due to parasitic bipolar junctions formed by subfins beneath semiconductor regions, which can cause data state fluctuations and single event upsets.
Innovation Solution
The formation of subfins with at least partially amorphized semiconductor material, such as silicon, is achieved through backside dopant implantation, particularly using germanium, to reduce the gain of parasitic devices and minimize charge amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistors are packed more densely to reduce integrated circuit size, then device spacing and circuit footprint are reduced, but parasitic effects and soft error rates increase
Solution Approach 1:
The patent applies local quality by amorphizing only the subfin regions beneath semiconductor devices while leaving other substrate regions crystalline. This localized modification targets the specific area where parasitic bipolar junctions form, reducing soft error rates without affecting the overall crystalline quality needed for device performance. The amorphized subfins locally eliminate the harmful parasitic effects while maintaining high-density transistor packing.
2Reliability
If subfins are amorphized to reduce parasitic current, then soft error rates decrease, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent employs preliminary action by performing ion implantation to amorphize subfins before final device assembly and operation. This advance modification eliminates parasitic bipolar junctions before they can cause soft errors, integrating the mitigation step into the fabrication flow rather than requiring additional complex structures or post-processing steps.
Solution Approach 2:
The patent changes the physical state parameter of the subfin material from crystalline to amorphous through ion implantation. This parameter change fundamentally alters the electrical properties of the subfin regions, eliminating parasitic current paths and reducing soft error rates. The transformation is achieved through controlled modification of material structure rather than adding complex device components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The amorphization of subfins reduces parasitic current and charge amplification, lowering soft error rates and maintaining transistor performance and reliability.
Implementation Method 1
A backside ion implantation process is performed to amorphize at least a portion of the subfin
Implementation Method 2
The amorphization has reliability, including radiation effects, benefits with minimal detrimental impact on transistor power and performance characteristics
Data Source
AI summary
Techniques to form semiconductor devices that include subfins that are at least partially amorphized are described. A backside dopant implantation process using dopants (e.g., germanium) may be used to create amorphous semiconductor material in the subfins. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region formed from a fin of semiconductor material. The fin includes a subfin laterally adjacent to a dielectric fill. A backside ion implantation process may be used to implant dopants such as Ge into the subfin and consequently form an amorphized portion of the subfin. In some examples, the amorphized portion is under the gate structure and laterally between a source region and a drain region. The amorphized portion may extend from a bottom surface of the subfin to just under the gate structure, and in some cases, leave a crystalline portion of subfin below the gate structure.