Deep-Trench MIM Capacitor With Amorphous Barrier for Lower Leakage
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Solution Overview
Problem
CMOS image sensors experience image lag and afterimage issues due to grain boundary defects, crystal defects, and interface traps in metal-insulator-metal (MIM) deep-trench capacitors, leading to decreased performance across frames of captured images.
Innovation Solution
Incorporating an amorphous material layer with a high bandgap energy level between the insulator layer stack and the capacitor bottom metal (CBM) layer in the MIM deep-trench capacitor structure to reduce electron tunneling and leakage, thereby improving lag performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric layers are used in MIM capacitors, then the device structure is simple and manufacturing is easier, but grain boundary defects, crystal defects, and interface traps cause electron tunneling and leakage leading to image lag and afterimage issues
Solution Approach 1:
The dielectric layer is segmented into multiple layers: a first dielectric layer with a first grain boundary structure, and a second dielectric layer with a second grain boundary structure. This segmentation allows each layer to be optimized independently, reducing overall leakage while maintaining manufacturability.
Solution Approach 2:
The patent uses composite dielectric materials with different properties in each layer. The first dielectric layer and second dielectric layer have different material compositions and grain boundary characteristics, creating a composite structure that reduces electron tunneling and leakage paths while improving lag performance.
2Reliability
If the insulator layer thickness is increased to reduce leakage, then electron tunneling is reduced, but the capacitor occupies more space and device area increases
Solution Approach 1:
Instead of using a single thick insulator layer, the patent divides the insulation function across multiple thinner dielectric layers. Each layer provides partial leakage reduction, achieving cumulative leakage suppression while maintaining a compact overall structure that fits within limited device area.
Solution Approach 2:
The composite dielectric structure with multiple layers of different materials provides enhanced leakage reduction per unit thickness compared to conventional single-material insulators. This allows achieving the same leakage reduction with reduced total thickness, preserving device area.
3Reliability
If multiple dielectric layers with different grain boundary structures are used to reduce leakage, then lag performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes specific parameters of each dielectric layer including thickness, material composition, and grain boundary orientation. By carefully controlling these parameters within realistic manufacturing tolerances, the design achieves superior lag performance without requiring extreme manufacturing precision that would be difficult to implement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The amorphous material layer effectively reduces leakage associated with grain boundaries and defects, enhancing the lag performance of CMOS image sensors without degrading breakdown voltage, making it suitable for various temperature conditions.
Implementation Method 1
The amorphous material includes a bandgap energy level that provides a conduction band offset and lowers a probability of electron tunneling from the CBM electrode layer to the insulator layer stack
Data Source
AI summary
Some implementations described herein provide a semiconductor device and methods of formation. The semiconductor device may include a photodiode device electrically connected to a metal-insulator-metal deep-trench capacitor. The metal-insulator-metal deep-trench capacitor includes a layer of an amorphous material between an insulator layer stack of the deep-trench capacitor structure and a capacitor bottom metal layer of the metal-insulator-metal deep-trench capacitor. The amorphous material includes a bandgap energy level that provides a conduction band offset and lowers a probability of electron tunneling from the capacitor bottom metal electrode layer to the insulator layer stack. In this way, leakage associated with grain boundaries, crystal defects, and interfaces of a bottom layer of the insulator layer stack may be overcome to improve a lag performance of the semiconductor device including the metal-insulator-metal deep-trench capacitor.