Amorphous Multi-Dielectric Gate Stack for Crystalline TFT Alignment
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Solution Overview
Problem
Current high-k dielectric materials are not suitable for crystalline thin film transistors due to their susceptibility to crystallization, which prevents self-alignment of semiconductor materials and results in poor electrostatic performance.
Innovation Solution
A multi-layer amorphous high-k gate dielectric stack is used, comprising alternating layers of high-k dielectric materials with thicknesses below the crystallization threshold, ensuring the dielectric remains amorphous and preventing crystallization, thereby allowing for improved electrostatic performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric materials are used to improve electrostatic performance, then electrostatic performance is improved, but the dielectric crystallizes and prevents self-alignment of semiconductor materials
Solution Approach 1:
The gate dielectric is divided into multiple alternating layers of different high-k dielectric materials (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide). Each layer has a thickness below the crystallization threshold, and the alternating composition prevents crystallization while maintaining high electrostatic performance.
Solution Approach 2:
The patent uses composite gate dielectric structures combining multiple high-k dielectric materials in alternating layers. This composite approach allows each material to contribute its high-k properties while the alternating structure prevents crystallization, achieving both improved electrostatic performance and maintained amorphous state stability.
2Reliability
If the thickness of high-k dielectric film is increased to minimize leakage current, then leakage current is reduced, but the film begins to crystallize
Solution Approach 1:
The total gate dielectric thickness needed for leakage minimization is segmented into multiple thinner alternating layers. Each individual layer remains below the crystallization threshold thickness, while the cumulative thickness provides sufficient leakage current minimization. The alternating composition ensures each layer stays amorphous.
Solution Approach 2:
The patent changes the compositional parameters by alternating between different high-k dielectric materials with varying crystallization thresholds. This parameter variation allows the structure to achieve effective thickness for leakage reduction while each individual layer maintains thickness below its specific crystallization threshold.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The amorphous high-k gate dielectric stack enhances electrostatic performance in crystalline thin film transistors by maintaining an amorphous state, preventing crystallization and allowing for self-alignment of semiconductor materials, thus improving device performance.
Implementation Method 1
as the thickness of a high-k dielectric film increases, the film begins to crystallize
Data Source
AI summary
Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.