Amorphous High-k Thin-Film Capacitors for First-Droop Reduction
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Solution Overview
Problem
Current solutions for minimizing first droop and power delivery noise in electronic devices, such as metal insulator metal capacitors and land-side capacitors, face limitations due to high-temperature requirements, manufacturing complexity, and increased package size and cost, especially when using ultra-high-k materials like PZT and BaTiO3.
Innovation Solution
The integration of thin film capacitors with amorphous high-k dielectric materials within the packaging substrate, which do not require high-temperature annealing and can be formed with minimal thickness, allowing for proximity to the die to effectively reduce first droop and power delivery noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ultra-high-k materials (PZT, BaTiO3) are used to improve first droop, then capacitance is improved, but high-temperature annealing (500°C or greater) is required which is not compatible with organic build-up materials and requires disruptive laser annealing
Solution Approach 1:
The patent changes the key parameter from ultra-high-k materials requiring high-temperature annealing to high-k dielectric materials that can be deposited at lower temperatures. The high-k dielectric layer is formed with a dielectric constant greater than 10 using techniques such as atomic layer deposition (ALD) or chemical vapor deposition (CVD) at temperatures compatible with organic build-up materials, eliminating the need for disruptive laser annealing processes
Solution Approach 2:
The patent uses composite material structures combining high-k dielectric materials with organic build-up materials. The capacitor structure integrates high-k dielectric layers with conductive layers and organic substrates, creating a composite system that achieves high capacitance while maintaining compatibility with standard organic package manufacturing processes
2Reliability
If ultra-high-k materials are used to improve first droop, then capacitance is improved, but the thickness must be 100 nm or greater to support crystal growth, limiting package form-factor
Solution Approach 1:
The patent changes the material parameter from ultra-high-k crystalline materials requiring thick films (100 nm or greater) to high-k dielectric materials that can achieve sufficient capacitance in thinner layers. The high-k dielectric layer can be formed with thicknesses between 10 nm and 100 nm while maintaining dielectric constants greater than 10, significantly reducing the Z-height and improving package form-factor
3Reliability
If prefabricated high-k dielectric films are used to integrate capacitors, then capacitance is improved, but the thickness (50 μm or greater) exceeds typical build-up layer thickness, increasing manufacturing complexity and Z-height
Solution Approach 1:
The patent segments the capacitor structure into multiple thin layers formed through sequential deposition processes. Instead of using a single thick prefabricated film (50 μm or greater), the capacitor is constructed with alternating thin layers of high-k dielectric material (10-100 nm) and conductive material, each layer being deposited in-situ using standard thin-film techniques compatible with build-up layer manufacturing
Solution Approach 2:
The patent changes the thickness parameter from micrometer-scale prefabricated films to nanometer-scale deposited layers. The high-k dielectric layer thickness is reduced to 10-100 nm, forming an integral part of the build-up layer structure rather than a separate thick component, thereby eliminating the need for additional lamination steps and reducing overall manufacturing complexity
4Reliability
If land-side capacitors are used to improve first droop, then capacitance is improved, but the electrical path is relatively long adding parasitic inductance and interfering with package/board interface
Solution Approach 1:
The patent merges the capacitor structure with the package substrate build-up layers, integrating capacitive elements directly into the power delivery network layers. The high-k dielectric layers and conductive layers forming the capacitor are deposited in-situ within the same build-up structure that contains the power and signal traces, eliminating the need for separate land-side capacitor components and their associated long electrical paths
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient reduction of first droop and power delivery noise while maintaining a compact form factor and compatibility with high-volume manufacturing processes, reducing parasitic inductance and interference with the package/board interface.
Implementation Method 1
thin film capacitors that are fabricated in the packaging substrate
Implementation Method 2
amorphous high-k dielectric materials
Data Source
AI summary
Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.