Amorphous Interface Film for Scaled FeRAM Memory Window Stability

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Solution Overview

Problem

Ferroelectric random-access memory (FeRAM) devices face challenges in maintaining memory window reliability as device sizes decrease, leading to increased device-to-device variations and difficulty in differentiating data states during read operations due to variations in orthorhombic phase distribution.

Innovation Solution

Incorporating an amorphous initiation layer in the ferroelectric data storage structure to influence the crystalline phase of the ferroelectric switching layer, resulting in a substantially uniform orthorhombic phase, which reduces device-to-device variations and improves read operation reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device size is decreased to improve integration density, then productivity increases, but device-to-device variations increase and memory window reliability deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidmemory window reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent changes the physical and chemical parameters of the ferroelectric material by introducing an amorphous initiation layer that controls the crystallization process. This layer modifies the phase transition behavior and orthorhombic phase distribution, enabling reliable ferroelectric operation at scaled dimensions where conventional materials fail

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The amorphous initiation layer serves as an intermediary between the substrate and the ferroelectric switching layer. It mediates the crystallization process by providing a controlled interface that promotes uniform orthorhombic phase formation, thereby reducing device-to-device variations and improving memory window reliability in scaled devices

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If device size is decreased to improve integration density, then productivity increases, but manufacturing precision deteriorates due to orthorhombic phase distribution variations

Engineering Contradiction:
Improveintegration densityVSAvoidorthorhombic phase distribution uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent modifies the crystallization parameters by introducing the amorphous initiation layer, which controls the phase transition temperature and kinetics. This enables precise control over orthorhombic phase distribution and crystal orientation, achieving uniform phase distribution even in miniaturized devices

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The amorphous initiation layer is formed beforehand to prepare the interface for subsequent ferroelectric material deposition. This preliminary structure controls the nucleation and growth of the orthorhombic phase, ensuring uniform phase distribution from the outset rather than attempting to correct variations after device fabrication

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The amorphous initiation layer enhances the ferroelectric response and memory window stability, allowing for scalable FeRAM devices with improved performance and reliability, even at smaller sizes.

Implementation Method 1

an amorphous initiation layer disposed on the lower electrode and separated from the upper electrode by the ferroelectric switching layer

Methodology Applied
Scientific EffectCrystallisation: Crystallisation

Data Source

PatentUS20240381663A1Interface film to mitigate size effect of memory device
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240381663A1 patent drawing
  • US20240381663A1 patent drawing
  • US20240381663A1 patent drawing

AI summary

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode structure and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.