Inductor Q Factor via Argon Implantation Amorphization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The quality factor of inductors in semiconductor devices is limited by high substrate losses, particularly due to accumulated charge at the silicon substrate and dielectric layer interface, which is not adequately addressed by existing methods that often require additional masking steps or post-fabrication process modifications, increasing costs and reducing the inductor's Q-factor for high-frequency applications.
Innovation Solution
Performing an ion implantation step to create an amorphous layer on the semiconductor substrate before the polysilicon layer is annealed, using heavy ions like Argon, without an additional masking step, thereby reducing substrate losses and enhancing the inductor's quality factor without degrading the polysilicon layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Argon implantation is performed after polysilicon processing (etching, resist stripping, annealing), then the polysilicon layer can be processed normally, but the polysilicon surface becomes damaged
Solution Approach 1:
The patent applies preliminary action by performing the Argon implantation step before polysilicon processing (etching, resist stripping, annealing) rather than after. This sequence ensures that the polysilicon layer is formed and processed while the amorphous layer is already in place to protect the substrate, preventing surface damage to the polysilicon during subsequent high-temperature annealing steps.
2Reliability
If an additional masking step is incorporated into the process, then polysilicon can be protected during Argon implantation, but manufacturing costs increase
Solution Approach 1:
The patent eliminates the need for additional masking steps by performing Argon implantation before polysilicon processing. The amorphous layer is created in advance to serve as a protective barrier, thereby protecting the polysilicon layer during subsequent processing without requiring extra masking operations, thus maintaining cost-effectiveness.
3Reliability
If thermal oxidation is used to grow dielectric layer on silicon substrate, then metallization layer is separated from substrate, but accumulated charge at interface increases substrate losses
Solution Approach 1:
The patent introduces an amorphous layer as an intermediary between the silicon substrate and the dielectric layer. This amorphous layer, created by Argon implantation, serves as a mediator that prevents charge accumulation at the silicon-dielectric interface while maintaining the isolation function. The intermediary layer effectively decouples the metallization from the substrate's lossy characteristics.
Solution Approach 2:
The patent changes the physical and electrical parameters of the substrate interface by transforming the crystalline silicon surface into an amorphous layer through ion implantation. This parameter change increases the effective resistance of the substrate at the interface region, thereby reducing RF losses while maintaining the necessary electrical isolation.
4Loss of energy
If high resistivity silicon is used to suppress substrate losses, then eddy currents are reduced, but Q-factor remains inadequate for high frequency applications
Solution Approach 1:
The patent applies local quality by creating an amorphous layer specifically at the substrate interface region where charge accumulation occurs, rather than uniformly modifying the entire substrate. This localized modification targets the specific problem area (the interface between substrate and dielectric) to reduce charge accumulation and improve Q-factor, while maintaining the overall high resistivity characteristics of the silicon substrate.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively increases the substrate resistance and improves the inductor's quality factor without additional masking steps or post-fabrication process complexities, enabling better RF performance for high-frequency applications while maintaining cost-effectiveness.
Implementation Method 1
performing an implantation process to implant into the substrate, heavy ions (typically Argon in the case of a Silicon substrate)
Implementation Method 2
create an amorphous layer on the substrate below the inductor
Implementation Method 3
the dielectric (SiO 2 ) layer which is grown on the silicon substrate by means of thermal oxidation
Implementation Method 4
the effective resistance of the substrate increased by the creation of an amorphous layer on the substrate below the inductor
Data Source
Figure 1~2
Figure 3
Figure 4a~4b
AI summary
A method of fabricating an inductor (70) in a silicon substrate (10), wherein an Argon implantation step (84) is performed after the resist layer (82) has been deposited and the polysiliconlayer (30) has been etched, but before the resist layer (82) is stripped and the polysilicon annealed. Thus, an amorphous layer (86) is created on the substrate (10) so as to improve the Q factor of the inductor (70), without the need for an additional masking step or adverse impact on the polysilicon layer (30).