Amorphous Layer Etching for Shallow Trench Isolation Air Gaps
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Solution Overview
Problem
The existing method for forming a large air gap in shallow trench isolation (STI) structures faces challenges due to high etching tolerance of sacrificial layers, making it difficult to achieve effective isolation in miniaturized integrated circuits.
Innovation Solution
The method involves forming an amorphous layer on the sidewalls of isolation trenches, burying a sacrificial layer within these trenches, and then removing the sacrificial layer to create an air gap, optimizing the etching process by controlling the thickness of the amorphous layer and etching conditions to enhance the etching rate and form a large air gap efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a sacrificial layer is used to form an air gap in STI structure, then the air gap can be formed, but the etching rate is too slow due to high etching tolerance of the sacrificial layer
Solution Approach 1:
The patent changes the physical and chemical parameters of the sacrificial layer by forming an amorphous silicon layer on its surface. This modifies the etching characteristics, enabling the sacrificial layer to be removed at an appropriate rate while maintaining structural integrity during formation. The amorphous silicon layer has different etching properties compared to the crystalline sacrificial layer material, resolving the contradiction between etching rate and etching tolerance.
Solution Approach 2:
The amorphous silicon layer acts as an intermediary between the sacrificial layer material and the etching process. It serves as a mediator that controls the etching rate, allowing the sacrificial layer to be removed at a manageable speed. This intermediary layer enables precise control over the air gap formation process while maintaining the sacrificial layer's structural stability during earlier processing steps.
2Volume of moving object
If the sacrificial layer thickness is increased to form a large air gap, then the air gap size increases, but the etching time becomes excessively long
Solution Approach 1:
By changing the etching parameters through the introduction of the amorphous silicon layer, the patent enables faster removal of the sacrificial layer. This parameter change allows large air gaps to be formed in reduced time, as the modified sacrificial layer etches at an optimized rate that balances gap size achievement with process efficiency.
Solution Approach 2:
The amorphous silicon layer is formed on the sacrificial layer surface before the etching process begins. This preliminary action modifies the surface properties to facilitate faster and more controlled etching, enabling the subsequent removal process to complete efficiently regardless of the sacrificial layer thickness required for the desired air gap size.
3Ease of manufacture
If conventional etching methods are used on the sacrificial layer, then the process is simple, but the etching rate is insufficient to form large air gaps efficiently
Solution Approach 1:
The patent applies a preliminary step of forming an amorphous silicon layer on the sacrificial layer surface before etching. This additional preliminary action, while adding a step to the process, enables dramatically improved etching rates that justify the added complexity. The modified process achieves large air gap formation in reduced time, balancing the trade-off between process simplicity and manufacturing productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the etching rate of the sacrificial layer, allowing for the formation of a large air gap in a shorter time, effectively addressing the challenge of high etching tolerance and improving isolation in semiconductor devices.
Implementation Method 1
forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer
Data Source
AI summary
In one embodiment, a method of manufacturing a semiconductor device includes forming an isolation trench in a substrate, and forming an amorphous layer on a sidewall surface of the isolation trench. The method further includes forming a sacrificial layer in the isolation trench via the amorphous layer, and forming an air gap layer on the sacrificial layer. The method further includes forming an air gap in the isolation trench under the air gap layer by removing the sacrificial layer after forming the air gap layer.