Amorphous Metal Oxide Interfacial Layer for MOS Transistors
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Solution Overview
Problem
The challenge in forming MOS transistors is the formation of interfacial layers with low dielectric constants when depositing high κ dielectrics, which increases the equivalent oxide thickness and reduces the efficiency of MOS transistors, particularly when using methods like sputtering and molecular beam epitaxy that lead to native oxide formation.
Innovation Solution
A method using molecular beam epitaxy in a reduced pressure environment to vaporize a solid-state metal-oxide source, forming an amorphous metal-oxide film on a semiconductor substrate without introducing oxygen, which serves as a diffusion barrier and nucleation layer, preventing interfacial layer formation and allowing for subsequent deposition of high κ dielectric films with reduced thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If high κ dielectrics are deposited directly on silicon substrate using sputtering or molecular beam epitaxy, then the dielectric constant is improved, but an interfacial oxide layer forms with low dielectric constant close to 4
Solution Approach 1:
The patent applies preliminary action by depositing a thin metal oxide layer (5-20 nm) on the silicon substrate before depositing the high κ dielectric. This preliminary metal oxide layer serves as an interfacial modification layer that prevents the formation of thick native oxide during subsequent high κ dielectric deposition, thereby maintaining low equivalent oxide thickness while enabling high dielectric constant materials to be deposited successfully.
Solution Approach 2:
The patent uses an intermediary metal oxide layer between the silicon substrate and the high κ dielectric. This intermediary layer acts as a buffer that prevents direct reaction between oxygen and silicon during high κ dielectric deposition, avoiding the formation of thick low-dielectric-constant interfacial oxide while still allowing good electrical contact and interface quality.
2Speed
If gate oxide thickness is reduced to increase device speed, then the operational speed is improved, but leakage current density increases beyond acceptable levels
Solution Approach 1:
The patent employs composite materials by combining a thin metal oxide interfacial layer with a high κ dielectric layer. This composite structure allows the gate dielectric to achieve both thin effective oxide thickness (for high speed) and high dielectric constant (for low leakage current). The metal oxide layer provides excellent interface quality while the high κ dielectric provides low leakage, achieving both goals simultaneously.
3Manufacturing precision
If molecular beam epitaxy is used to deposit metal oxide, then the film quality is improved, but oxygen injection causes native oxide formation on substrate surface
Solution Approach 1:
The patent segments the deposition process into two distinct stages: first depositing a thin metal oxide interfacial layer using molecular beam epitaxy under controlled conditions, then depositing the high κ dielectric layer separately. This segmentation allows the first stage to create a high-quality interface without excessive oxide formation, while the second stage adds the high dielectric constant material, solving both film quality and native oxide formation issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the thickness of interfacial layers, enhances the dielectric properties, and decreases leakage current, thereby improving the efficiency and performance of MOS transistors by preventing native oxide formation and providing a superior nucleation surface for further high κ dielectric deposition.
Implementation Method 1
vaporize a solid-state metal-oxide source to deposit, in the form of oxide molecules or their clusters, a first metal-oxide film
Implementation Method 2
in a reduced pressure environment having a pressure lower than 1×10−6 Torr... the surface of the substrate will not be oxidized to form a native oxide film
Implementation Method 3
forming an amorphous metal-oxide film... which serves as a diffusion barrier and nucleation layer, preventing interfacial layer formation
Implementation Method 4
forming an amorphous metal-oxide film... which serves as a diffusion barrier and nucleation layer, providing a superior nucleation surface for further high κ dielectric deposition
Data Source
AI summary
The present invention provides a method for forming substrates for MOS (metal oxide semiconductor) transistor, comprising the following steps: (A) In a reduced-pressure environment having a pressure lower than 1×10−6 Torr, a base for accomplishing the surface reconstruction and a solid-state metal oxide source is provided, wherein the solid-state metal oxide source is chosen from the group consisting of the following: hafnium oxide, aluminum oxide, scandium oxide, yttrium oxide, titanium oxide, gallium gadolinium oxide and metal oxides of rare earth elements; and (B) vaporize the solid-state metal oxide source in order to make the solid-state metal oxide source become a metal oxide molecular beam and, in a working substrate temperature that is required to achieve an amorphous state of a first metal oxide film, deposit on the base having an amorphous state so as to further fabricate a substrate for MOS transistors.