Amorphous Polysilicon Fin Trenches to Reduce Seam Defects
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Solution Overview
Problem
The formation of seams and defects in polycrystalline silicon-filled trenches between fin transistors in semiconductor manufacturing poses challenges due to non-rectangular trench shapes and tilted sidewalls, leading to potential defects and reliability issues in finFET devices.
Innovation Solution
A method involving the formation of amorphous polysilicon over a dielectric layer in the trenches, using a low-temperature chemical vapor deposition process to minimize grain size and reduce seam defects, followed by a selective etch to form a gate conductor, which reduces the likelihood of voids and oxide formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional high-temperature polysilicon deposition is used to fill trenches, then complete trench filling is achieved, but large grain sizes form causing seam defects and voids
Solution Approach 1:
The patent changes the deposition temperature parameter from conventional high temperature to low temperature (below 450°C), which fundamentally alters the grain growth behavior of polysilicon. This parameter change enables complete trench filling while maintaining fine grain sizes that prevent seam defect formation, resolving the contradiction between filling completeness and reliability.
Solution Approach 2:
The patent utilizes the phase transition characteristics of polysilicon deposition at low temperatures, where the material deposits in an amorphous or fine-grained crystalline state rather than forming large grains. This phase behavior difference allows the polysilicon to conform to complex trench geometries without the harmful grain boundary formation that occurs at higher temperatures.
2Quantity of substance
If polysilicon is deposited at high temperature, then material fills trenches effectively, but oxygen diffusion increases creating oxide defects
Solution Approach 1:
By changing the deposition temperature parameter to below 450°C, the patent simultaneously achieves adequate polysilicon filling while suppressing oxygen diffusion. The lower temperature reduces the kinetic energy of atoms, preventing oxygen from diffusing into the polysilicon lattice and forming harmful oxide defects, thus resolving the contradiction between material quantity and harmful factor generation.
3Ease of manufacture
If standard etching processes are used on polysilicon-filled trenches, then gate conductors are formed, but selectivity issues cause defects
Solution Approach 1:
The patent changes the physical and chemical properties of the polysilicon layer through low-temperature deposition, creating a material with distinct etch characteristics. This parameter change in material structure enables highly selective etching processes that can remove the polysilicon gate conductor material without affecting adjacent dielectric or semiconductor layers, resolving the selectivity issue.
Solution Approach 2:
The patent creates a composite structure where low-temperature polysilicon with fine grain structure is deposited over the trench region. This composite material approach, combined with the dielectric layer, provides differential etch responses that enable selective removal of polysilicon while preserving surrounding structures, improving manufacturing precision during gate conductor formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes seam defects and voids in the polysilicon layer, enhancing the reliability and consistency of finFET devices by preventing oxygen diffusion and maintaining high selectivity in the etching process, thus improving the overall performance and reducing defects in the semiconductor structure.
Implementation Method 1
using a low-temperature chemical vapor deposition process to minimize grain size and reduce seam defects
Implementation Method 2
minimizes seam defects and voids in the polysilicon layer, enhancing the reliability and consistency of finFET devices by preventing oxygen diffusion
Data Source
AI summary
Forming an integrated circuit by first, forming a first fin and a second fin from a semiconductor layer, with an area between the first fin and the second fin, second, forming a dielectric layer covering at least a portion of the first fin, at least a portion of the second fin, and at least a portion of the area, and third, forming amorphous polysilicon covering a least a portion of the dielectric layer.