Amorphous Region Below Source-Drain Patterns for Leakage Control

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Solution Overview

Problem

As semiconductor devices are scaled down, the operating characteristics deteriorate due to high integration, leading to challenges in achieving superior performance.

Innovation Solution

The semiconductor device incorporates a substrate with a device isolation layer defining active patterns, source/drain patterns, and a channel pattern, where an amorphous region is positioned below the source/drain patterns to prevent dopant diffusion and improve electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MOSFET sizes are scaled down to achieve high integration, then device density increases, but operating characteristics deteriorate

Engineering Contradiction:
Improvedevice integration densityVSAvoidoperating characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an amorphous region with specific physical properties (amorphous phase) localized below the source/drain patterns. This creates a spatially differentiated structure where the amorphous region provides dopant diffusion suppression while other regions maintain their original crystalline structure and electrical properties, thus improving reliability without compromising integration density

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The amorphous region acts as an intermediary layer between the source/drain patterns and the active pattern. It mediates the interaction by suppressing dopant diffusion from the source/drain regions into the active pattern, thereby preventing harmful dopant contamination while maintaining the scaled-down device dimensions

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If source/drain patterns are formed with standard width, then manufacturing is simplified, but dopant diffusion increases causing current leakage

Engineering Contradiction:
Improvesource/drain pattern fabricationVSAvoiddopant diffusion and current leakage
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The amorphous region serves as a physical barrier and intermediary that blocks dopant diffusion paths. It is positioned between the source/drain patterns and the active pattern, effectively stopping dopant migration without requiring changes to source/drain pattern dimensions or manufacturing processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the physical state parameter of the semiconductor material from crystalline to amorphous in the region below the source/drain patterns. This phase change creates a material with different diffusion properties that suppress dopant migration, thereby reducing current leakage while maintaining standard source/drain pattern dimensions

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The amorphous region effectively suppresses dopant diffusion, minimizing current leakage and enhancing the electrical performance of the semiconductor device.

Implementation Method 1

an amorphous region positioned below the source/drain patterns to prevent dopant diffusion

Methodology Applied
Scientific EffectDopant diffusion suppression: Diffusion Barrier

Data Source

PatentUS11563089B2Method for manufacturing a semiconductor device
Publication Date: 2023.01.24 SAMSUNG ELECTRONICS CO LTD
  • US11563089B2 patent drawing
  • US11563089B2 patent drawing
  • US11563089B2 patent drawing

AI summary

A semiconductor device includes a substrate, a device isolation layer on the substrate, the device isolation layer defining a first active pattern, a pair of first source/drain patterns on the first active pattern, the pair of first source/drain patterns being spaced apart from each other in a first direction, and each of the pair of first source/drain patterns having a maximum first width in the first direction, a first channel pattern between the pair of first source/drain patterns, a gate electrode on the first channel pattern and extends in a second direction intersecting the first direction, and a first amorphous region in the first active pattern, the first amorphous region being below at least one of the pair of first source/drain patterns, and having a maximum second width in the first direction that is less than the maximum first width.