Amorphous Silicon Cap Layer Mitigates Boron Channeling in SiGe MOS Devices
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Solution Overview
Problem
The existing manufacturing processes for semiconductor devices using silicon germanium (SiGe) epitaxy material face limitations due to boron channeling effects and damage from ion implantation, which can degrade device performance.
Innovation Solution
A method is introduced that involves forming a semiconductor device structure with a silicon germanium (SiGe) layer covered by an amorphous silicon cap layer, using in-situ boron doping selective epitaxy growth, and performing ion implantation followed by annealing, to mitigate boron channeling effects and enhance device performance by managing stress and implantation damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ion implantation is performed to form source/drain regions, then dopant concentration is improved, but boron channeling effects and implantation damage occur
Solution Approach 1:
An amorphous silicon cap layer is formed on the SiGe layer before ion implantation. This preliminary action creates a protective barrier that prevents boron channeling effects and reduces implantation damage while still allowing dopant diffusion to achieve the desired concentration in the source/drain regions.
Solution Approach 2:
The amorphous silicon cap layer serves as an intermediary between the ion implantation process and the SiGe layer. It mediates the harmful effects of direct ion bombardment on the SiGe crystal structure while still permitting controlled dopant diffusion to occur, thus protecting the underlying layer during the doping process.
2Reliability
If SiGe layer is formed to enhance carrier mobility, then device performance is improved, but stress management becomes complex due to metal silicide layer formation
Solution Approach 1:
The patent replaces the mechanical stress management approach with a chemical/compositional approach. Instead of relying solely on the mechanical properties of the SiGe layer and metal silicide combination, the amorphous silicon cap layer provides stress control through its material properties and interface characteristics, simplifying the overall stress management mechanism.
Solution Approach 2:
The structure utilizes composite materials with the amorphous silicon cap layer combined with the crystalline SiGe layer. This composite structure allows for optimized stress distribution and carrier mobility enhancement while managing the interactions between different materials to achieve desired device performance without excessive complexity.
3Object-affected harmful factors
If amorphous silicon cap layer is formed to cover SiGe layer, then boron channeling effects are reduced, but process complexity increases
Solution Approach 1:
The patent changes the physical state parameter of the cap layer by using amorphous silicon instead of crystalline silicon. This parameter change is crucial because the amorphous structure effectively prevents boron channeling effects that occur in crystalline structures, while the deposition process remains relatively straightforward and compatible with existing manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by reducing boron channeling effects, sustaining strain in the SiGe layer, and alleviating implantation damage, resulting in enhanced mobility and reliability of the semiconductor device.
Implementation Method 1
performing an ion implantation process to form a pair of source/drain regions in the silicon germanium layer
Implementation Method 2
a selective epitaxy growth process is performed to form a silicon germanium (SiGe) layer filling the trenches
Implementation Method 3
an annealing process can be further performed after the ion implantation process to active the implanted ions
Data Source
AI summary
A method for forming a metal-oxide-semiconductor (MOS) device includes at least steps of forming a pair of trenches in a substrate at both sides of a gate structure, filling the trenches with a silicon germanium layer by a selective epitaxy growth process, forming a cap layer on the silicon germanium layer by a selective growth process, and forming a pair of source/drain regions by performing an ion implantation process. Hence, the undesirable effects caused by ion implantation can be mitigated.