Amorphous Silicon Capacitor Stepped Hole Fabrication
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Solution Overview
Problem
The miniaturization of semiconductor devices requires capacitors with smaller footprints, leading to decreased capacitance due to smaller cylindrical hole diameters, which is challenging to compensate for without compromising the depth and shape of the hole during etching, resulting in insufficient capacitance in inverted truncated cone-shaped holes.
Innovation Solution
A semiconductor device fabrication method involving laminating multiple amorphous silicon films with varying etching rates, where a faster etching rate first amorphous silicon film is interposed between a slower etching rate second amorphous silicon film, allowing for stepped portions and increased inner surface area without enlarging the hole's diameter, thus maintaining capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the diameter of the cylindrical hole is decreased to reduce capacitor footprint, then the area occupied by the capacitor is reduced, but the capacitance decreases due to smaller inner surface area
Solution Approach 1:
The invention transitions from a simple cylindrical hole to a stepped-hole structure by introducing multiple depth levels. The hole comprises a first hole portion and a second hole portion with different depths, creating stepped inner surfaces. This dimensional change in the depth direction increases the total inner surface area available for capacitor electrodes without increasing the footprint area, thereby maintaining capacitance while reducing capacitor size.
Solution Approach 2:
The cylindrical hole is segmented into multiple portions (first hole portion and second hole portion) with different depths and diameters. Each portion contributes to the total inner surface area, allowing the capacitor to achieve sufficient capacitance through the combined surface area of multiple segmented regions rather than relying on a single large cylindrical surface.
2Quantity of substance
If the depth of the cylindrical hole is increased to compensate for decreased capacitance, then the inner surface area increases, but the etching process becomes problematic due to diameter decrease in the direction of etching advance
Solution Approach 1:
The invention uses a plug structure formed in advance within the hole before the final etching process. The plug is positioned to prevent etching solution from reaching certain regions, allowing selective formation of the stepped hole portions. This preliminary action enables precise control over the hole shape and depth distribution, solving the problem of uncontrolled diameter decrease during deep etching.
Solution Approach 2:
The plug acts as an intermediary element that mediates the etching process. By placing the plug at specific positions within the hole, it controls the flow of etching solution and prevents over-etching in certain regions. This intermediary structure enables the formation of the desired stepped hole shape with precise depth control, overcoming the limitations of direct deep etching.
3Device complexity
If a single-layer structure is used, then the fabrication process is simpler, but the inner surface area is insufficient to maintain capacitance at small footprints
Solution Approach 1:
The invention introduces a vertical dimension with multiple hole portions at different depths, creating a stepped structure. This multi-level configuration increases the inner surface area without proportionally increasing the footprint area, achieving sufficient capacitance in a compact form factor while maintaining relatively simple fabrication processes.
Solution Approach 2:
The stepped hole structure can be viewed as a nested configuration where the second hole portion is positioned within the overall hole structure at a different depth level. This nesting approach maximizes the use of vertical space to increase surface area for capacitance while maintaining a compact footprint, effectively solving the contradiction between device complexity and capacitance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively increases the inner surface area of the through-hole while preventing area expansion, ensuring sufficient capacitance in capacitors formed within the semiconductor device, even at smaller sizes.
Implementation Method 1
subjecting the plurality of amorphous silicon films having the through-hole to an etching process by an alkaline aqueous solution
Data Source
AI summary
The semiconductor device fabrication method of the present invention includes: laminating a plurality of amorphous silicon films on a semiconductor substrate, forming through-holes that pass through the plurality of amorphous silicon films, and subjecting the plurality of amorphous silicon films 301 that include the through-holes to an etching process that uses an alkaline aqueous solution; wherein the plurality of amorphous silicon films is formed to include a first amorphous silicon film and a second amorphous silicon film in which the rate of etching by using the alkaline aqueous solution is slower than that of the first amorphous silicon film and the first amorphous silicon film is interposed between the semiconductor substrate and the second amorphous silicon film.