Amorphous Silicon Capping Layer EOT Reduction
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce the effective oxide thickness (EOT) of film stacks in FinFETs while preventing amorphous silicon (a-Si) agglomeration during high-temperature annealing, which causes non-uniformity and reduces device reliability.
Innovation Solution
Depositing an amorphous silicon capping layer atop a titanium nitride layer within a film stack, followed by treatment with a nitrogen-containing gas such as hydrazine, and then annealing at temperatures between 700°C to 1000°C to prevent a-Si agglomeration and maintain uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-temperature annealing is performed to reduce effective oxide thickness, then EOT reduction is achieved, but amorphous silicon agglomeration occurs causing non-uniformity
Solution Approach 1:
A nitrogen-containing layer is formed on the amorphous silicon capping layer before the high-temperature annealing process. This preliminary action creates a protective barrier that prevents silicon agglomeration during subsequent annealing, allowing EOT reduction to proceed without compromising uniformity or reliability.
Solution Approach 2:
The nitrogen-containing layer acts as an intermediary between the amorphous silicon capping layer and the high-temperature annealing environment. It mediates the interaction by providing nitrogen atoms that suppress silicon diffusion and agglomeration, enabling the annealing process to reduce EOT while maintaining film integrity.
2Manufacturing precision
If amorphous silicon capping layer is used to reduce EOT, then EOT reduction is achieved, but silicon agglomeration occurs during annealing
Solution Approach 1:
The nitrogen-containing layer is deposited beforehand to establish a protective interface. This preliminary configuration ensures that when annealing occurs, nitrogen atoms are already in position to prevent silicon atom migration and agglomeration, maintaining compositional stability throughout the EOT reduction process.
Solution Approach 2:
The potential harmful effect of high-temperature annealing on amorphous silicon (causing agglomeration) is converted into a beneficial process. By introducing the nitrogen-containing layer, the annealing temperature can be optimized to achieve EOT reduction while the nitrogen simultaneously prevents the harmful agglomeration effect.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the EOT by 0.5 to 2 angstroms, ensuring uniformity and reliability of the semiconductor device, suitable for advanced technology nodes like 7 nm and beyond.
Implementation Method 1
contacting the top surface of the amorphous silicon capping layer with a nitrogen containing gas
Implementation Method 2
annealing the film stack
Implementation Method 3
annealing at temperatures between 700°C to 1000°C
Data Source
AI summary
Methods and apparatus for forming a semiconductor structure with a scaled effective oxide thickness is disclosed. In embodiments, a method includes depositing amorphous silicon capping layer having a first surface atop a first surface of a titanium nitride (TiN) layer, wherein the titanium nitride layer is atop a first surface of a high-k dielectric layer disposed within a film stack; contacting the first surface of the amorphous silicon capping layer with a nitrogen containing gas; and annealing the film stack.