Amorphous Silicon Gate Electrodes for CMOS CD Bias Reduction
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Solution Overview
Problem
The existing CMOS fabrication processes result in a critical dimension (CD) bias between NMOS and PMOS transistors due to differing etch rates of n-doped and undoped polysilicon gate electrodes, leading to variations in channel lengths and undesirable performance.
Innovation Solution
The method involves depositing a polysilicon layer over a semiconductor body, performing a first type implant in one region and an amorphizing implant in both regions to convert the polysilicon into an amorphous silicon layer, which is then patterned to form gate electrodes, thereby reducing the etch rate differences and eliminating the CD bias between NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If n-type implant is performed into polysilicon layer in NMOS region to reduce resistivity, then electrical conductivity is improved, but etch rate increases causing gate CD bias
Solution Approach 1:
The patent changes the physical state of the polysilicon layer from crystalline to amorphous through amorphizing implant. This parameter change makes the etch rate insensitive to doping differences, thereby eliminating gate CD bias while preserving the electrical conductivity improvements from n-type implant in NMOS region.
Solution Approach 2:
Instead of trying to make etch rates different to accommodate doping differences, the patent inverts the approach by making both regions have the same amorphous structure, which causes them to etch at the same rate regardless of doping differences. This reverses the conventional thinking of matching etch rates through doping control.
2Reliability
If polysilicon is doped to reduce resistivity, then gate electrode conductivity is improved, but poly depletion effect increases EOT
Solution Approach 1:
The patent changes the crystalline structure of polysilicon to amorphous form, which alters the electrical properties and eliminates poly depletion effect. The amorphous structure provides different conduction mechanisms that reduce EOT increase while maintaining conductivity through the amorphous doped layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach substantially reduces the gate CD bias by making the etch rates of the amorphous silicon layers in both regions more similar, resulting in consistent gate electrode dimensions and improved transistor performance.
Implementation Method 1
performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer
Implementation Method 2
performing a first type implant into the polysilicon layer in one of the NMOS region and the PMOS region
Data Source
AI summary
A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.