Amorphous Silicon Gap Filling Void Elimination
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Solution Overview
Problem
Semiconductor devices often exhibit voids or seams in silicon-filled gaps due to non-uniform deposition processes, which can impact the performance of electronic devices.
Innovation Solution
A method involving the deposition of an amorphous silicon film at a temperature between 300 and 500°C with a hydrogen concentration of 0.1-10 at.%, followed by exposure to a silicon mobility inhibitor and subsequent annealing to reduce or eliminate voids without crystallizing the silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a silicon layer is deposited to fill gaps from sides and bottom, then the gap filling is achieved, but voids and seams form in the interior of the filled gap
Solution Approach 1:
The patent changes the deposition temperature parameter to between 300-500°C and controls hydrogen concentration at 0.1-10 at.% to deposit amorphous silicon instead of crystalline silicon. This parameter change modifies the deposition kinetics to achieve more uniform growth that prevents void and seam formation in the gap interior.
Solution Approach 2:
The patent utilizes the phase state of silicon by depositing amorphous silicon (non-crystalline phase) rather than crystalline silicon. The amorphous phase allows for more uniform deposition and better gap filling without the directional growth patterns that cause voids and seams in crystalline silicon deposition.
2Manufacturing precision
If the substrate is annealed at high temperature to reduce voids, then void reduction is achieved, but the silicon crystallizes causing surface roughness
Solution Approach 1:
The patent performs annealing at temperatures between 500-700°C, which is carefully controlled to reduce voids through atomic diffusion while staying below the crystallization temperature of amorphous silicon. This parameter control allows void reduction without triggering the phase transition to crystalline silicon that would cause surface roughness.
Solution Approach 2:
The patent converts the potential harm of high-temperature annealing (which would cause crystallization) into a benefit by utilizing the amorphous silicon's unique property of remaining amorphous even after annealing at temperatures that would crystallize conventional silicon. The hydrogen content in the amorphous silicon suppresses crystallization while allowing void reduction through thermal diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively fills gaps with minimal or no voids, maintaining the amorphous morphology of the silicon fill and ensuring a smooth surface, while preventing unwanted crystallization and roughness during etching processes.
Implementation Method 1
depositing an amorphous silicon film onto the substrate having a thickness sufficient to fill the gap... providing a feed gas that comprises a first silicon reactant to deposit silicon forming the amorphous silicon film
Implementation Method 2
heating the substrate to a deposition temperature between 300 and 500° C.... subsequently reducing a size of the void by annealing the silicon film... annealed at an anneal temperature between 500 and 700° C.
Data Source
AI summary
Amorphous silicon-filled gaps may be formed having no or a low occurrence of voids in the amorphous silicon fill, while maintaining a smooth exposed silicon surface. A gap in a substrate may be filled with amorphous silicon by heating the substrate to a deposition temperature between 300 and 500° C. and providing a feed gas that comprises a first silicon reactant to deposit an amorphous silicon film into the gap with an hydrogen concentration between 0.1 and 10 at. %. The deposited silicon film may subsequently be annealed. After the anneal, any voids may be reduced in size and this reduction in size may occur to such an extent that the voids may be eliminated.