Amorphous Silicon Gate Pattern for Boron Penetration Control
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Solution Overview
Problem
Semiconductor devices with polysilicon gate patterns face issues of impurity depletion and boron penetration, leading to increased threshold voltage and reduced on-current due to insufficient doping in the lower portion of the polysilicon gate, which degrades the electrical characteristics of MOS transistors.
Innovation Solution
A semiconductor device and method involving a gate insulation pattern with a semiconductor gate pattern comprising an amorphous silicon pattern and a polycrystalline silicon pattern, where the amorphous silicon pattern is doped with anti-diffusion impurities such as nitrogen, carbon, or oxygen atoms to suppress impurity diffusion and crystallization, ensuring sufficient impurity concentration and minimizing etch damage during fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a polysilicon layer is used as gate electrode material, then the device can be fabricated with standard processes, but impurity depletion and boron penetration occur leading to increased threshold voltage and reduced on-current
Solution Approach 1:
The gate electrode is divided into two distinct layers: a bottom polysilicon layer and a top amorphous silicon layer. This segmentation allows each layer to perform different functions - the bottom layer provides structural support and can be doped, while the top layer acts as an impurity barrier, preventing boron penetration and maintaining stable electrical characteristics.
Solution Approach 2:
The gate electrode uses a composite structure combining polysilicon and amorphous silicon materials. This composite approach leverages the advantages of both materials - polysilicon's ease of fabrication and amorphous silicon's superior impurity blocking properties - to achieve both manufacturability and reliable electrical performance.
2Object-affected harmful factors
If the polysilicon gate thickness is reduced to minimize etch damage, then etch damage is reduced, but insufficient doping in the lower portion occurs leading to impurity depletion
Solution Approach 1:
The solution moves from a single-dimensional thickness adjustment to a two-dimensional approach by adding a vertical layer structure. Instead of relying solely on reducing thickness to minimize etch damage, a new dimension (layer stacking) is introduced where the top amorphous silicon layer provides impurity blocking functionality without requiring significant thickness reduction of the bottom polysilicon layer.
Solution Approach 2:
Different regions of the gate electrode are assigned different properties: the bottom polysilicon layer is optimized for doping and structural support, while the top amorphous silicon layer is optimized for impurity barrier functionality. This local quality differentiation allows each layer to be optimized for its specific function, ensuring sufficient doping in the bottom layer while maintaining effective impurity blocking at the top.
3Reliability
If anti-diffusion impurities are doped into the amorphous silicon pattern, then impurity diffusion is suppressed, but the fabrication process complexity increases
Solution Approach 1:
Anti-diffusion impurities (such as nitrogen or carbon) are doped into the amorphous silicon layer during its deposition process, before subsequent processing steps. This preliminary doping action ensures impurity barrier functionality is established early, and the same deposition step simultaneously achieves both material formation and impurity incorporation, reducing the need for additional separate doping steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses impurity depletion and boron penetration, stabilizing the threshold voltage and enhancing the on-current of MOS transistors by ensuring high impurity concentrations in the semiconductor gate pattern, thereby improving the electrical characteristics and reducing sheet resistance.
Implementation Method 1
an amorphous silicon pattern and a polycrystalline silicon pattern, wherein the amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern
Implementation Method 2
The anti-diffusion impurities may suppress crystallization of the first amorphous silicon layer and the second amorphous silicon layer is selectively crystallized
Data Source
AI summary
A semiconductor device including a gate insulation pattern on a substrate, and a semiconductor gate pattern including an amorphous silicon pattern and a polycrystalline silicon pattern stacked on a side of the gate insulation pattern opposite to the substrate. The amorphous silicon pattern includes anti-diffusion impurities that suppress diffusion of impurity ions in the semiconductor gate pattern.