Amorphous Silicon Gate Structure for MOSFET Leakage Reduction
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Solution Overview
Problem
Conventional MOSFET fabrication techniques face issues with dopant penetration through the silicon dioxide layer into the silicon substrate, leading to shifts in electric characteristics and current leakage due to the presence of grain boundaries in polysilicon layers, requiring additional un-doped polysilicon layers to mitigate these issues but still resulting in inefficiencies.
Innovation Solution
A fabrication method using an amorphous silicon layer with a gate dielectric layer, where an un-doped amorphous silicon layer is formed first, followed by a doped amorphous silicon layer, both within a controlled temperature range of 520° C. to 560° C. in an in situ chamber, eliminating grain boundaries and reducing dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon layers are used to form the gate structure, then the gate structure can be formed with conventional LPCVD processes, but dopant ions penetrate through the silicon dioxide layer into the silicon substrate causing shift in electric characteristics
Solution Approach 1:
The patent changes the material parameter from polysilicon to amorphous silicon, which fundamentally alters the structural properties (eliminating grain boundaries) while maintaining compatibility with existing LPCVD fabrication processes. This parameter change prevents dopant penetration without requiring process redesign
Solution Approach 2:
The amorphous silicon layer acts as an intermediary between the doped polysilicon gate and the silicon dioxide layer, providing a barrier that prevents dopant ions from penetrating into the substrate while still allowing the gate structure to function properly
2Reliability
If an un-doped polysilicon layer is added to prevent dopant penetration, then dopant diffusion is reduced, but the device complexity and fabrication process become more complex
Solution Approach 1:
Instead of adding more layers (increasing complexity), the patent changes the material parameter of the existing silicon layer from crystalline polysilicon to amorphous silicon. This single parameter change eliminates grain boundaries and prevents dopant penetration without requiring additional layers or complex structures
3Stability of the object's composition
If polysilicon is deposited at high temperature (600-650°C), then the deposited silicon forms polysilicon structure, but this requires higher fabrication temperature and more energy
Solution Approach 1:
The patent changes the temperature parameter from 600-650°C to 500-550°C, which shifts the material formation from polysilicon to amorphous silicon. This parameter change reduces energy consumption while still achieving a stable, functional gate structure without requiring high-temperature crystallization
Solution Approach 2:
The patent utilizes the phase transition behavior of silicon during deposition, controlling the temperature to produce amorphous silicon instead of crystalline polysilicon. This phase transition approach allows lower deposition temperatures while maintaining structural integrity for gate formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces current leakage, improves electric characteristics, and enhances manufacturing efficiency by forming both amorphous silicon layers in the same chamber, resulting in improved MOSFET performance with reduced dopant diffusion and lower fabrication temperatures.
Implementation Method 1
an amorphous silicon layer of a first selected thickness is formed on the substrate layer under a reaction temperature between about 520° C. and 560° C.
Implementation Method 2
the polysilicon is formed through low pressure chemical vapor deposition (LPCVD) by heating and decomposing silane (i.e., SiH4). The reaction formula is as follow: SiH4(g)→Si(s)+2H2(g)
Implementation Method 3
a doped amorphous silicon layer of a second selected thickness is formed on the amorphous silicon layer under a reaction temperature between about 520° C. and 560° C.
Data Source
AI summary
A fabrication method for forming a gate structure through an amorphous silicon layer includes providing a substrate layer, forming an amorphous silicon layer of a selected thickness on the substrate layer at a reaction temperature between about 520° C. and 560° C., and forming a doped amorphous silicon layer in a upper portion of the amorphous silicon layer at a reaction temperature between about 520° C. and 560° C.