Amorphous Silicon Gate Structure for EEPROM Speed and Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The performance of EEPROM non-volatile memory devices is limited by the rate of electron pumping and erasing, which can damage smaller tunneling oxide layers, and there is a need for improved processing strategies to achieve smaller memory devices with greater uniformity and operational performance.
Innovation Solution
A gate structure for semiconductor devices comprising a dielectric layer, an amorphous silicon layer, and a conductive layer, where the amorphous silicon layer is disposed between the dielectric and conductive layers to reduce dielectric encroachment and enhance the gate coupling ratio, with the amorphous silicon layer formed using chemical vapor deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the tunneling oxide layer is made thinner to increase data writing and erasing efficiency and speed, then the programming speed and writing efficiency are improved, but the layer becomes more susceptible to damage upon exposure to recording or erasing energies
Solution Approach 1:
The patent introduces a composite dielectric structure consisting of multiple oxide layers (first oxide layer, second oxide layer) with different thicknesses and compositions. This composite structure allows the tunneling region to maintain thin dimensions for high-speed operation while the overall dielectric layer provides enhanced durability and resistance to damage from recording/erasing energies, thus resolving the contradiction between speed and reliability
Solution Approach 2:
The patent applies local quality by creating a non-uniform dielectric structure where the first oxide layer has a different thickness than the second oxide layer. The thinner first oxide layer enables efficient electron tunneling for fast programming, while the thicker second oxide layer provides protection against damage, allowing different regions of the dielectric to serve different functional requirements simultaneously
2Volume of moving object
If the dimensions of memory devices are reduced to achieve smaller devices, then the device size is reduced, but greater uniformity in memory device layers is required to ensure device performance
Solution Approach 1:
The patent segments the dielectric layer into multiple distinct oxide layers with specific thicknesses and compositions. This segmentation allows each layer to be optimized independently for uniformity control during manufacturing, making it easier to achieve the required precision in smaller devices compared to attempting to uniformize a single thick dielectric layer
Solution Approach 2:
By using composite dielectric materials with different oxide compositions and thicknesses, the patent creates a structure that is more tolerant to manufacturing variations. The multi-layer composite structure allows for better control of overall uniformity even when device dimensions are reduced, as each layer can be deposited and controlled separately
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces dielectric encroachment, improves the gate coupling ratio, and enhances the speed and efficiency of writing and erasing operations in EEPROM devices, leading to improved operational performance and reliability.
Implementation Method 1
the amorphous silicon layer formed using chemical vapor deposition techniques
Data Source
AI summary
An improved semiconductor device results from the use of an amorphous silicon layer in a gate structure disposed between a dielectric layer and an upper conductive layer such as a control gate. Both a semiconductor device and method of manufacturing a semiconductor device using an amorphous silicon layer are provided.