Amorphous Silicon Hard Mask for High-k Gate Patterning
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Solution Overview
Problem
Transistors with high-k gate insulation layers and polysilicon gate electrodes face issues with increased threshold voltage and decreased electron mobility due to the Fermi-level pinning effect, necessitating improved manufacturing methods for better electrical performance.
Innovation Solution
The method involves forming a gate insulation layer with a high-k dielectric material, an etch stop layer, and a metal layer, followed by patterning using a hard mask of amorphous silicon, which helps in preventing direct contact between polysilicon and the high-k layer, thereby reducing the Fermi-level pinning effect and enhancing electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate electrode including polysilicon is formed directly on the gate insulation layer including high-k material, then the manufacturing process is simple, but the transistor has increased threshold voltage and decreased electron mobility due to Fermi-level pinning effect
Solution Approach 1:
An etch stop layer is introduced as an intermediary between the high-k gate insulation layer and the metal gate electrode. This etch stop layer prevents direct contact between the polysilicon and high-k material, thereby eliminating the Fermi-level pinning effect while maintaining manufacturing feasibility. The etch stop layer serves as a mediator that resolves the electrical performance issue without significantly complicating the manufacturing process.
2Reliability
If a metal gate electrode is formed to avoid Fermi-level pinning effect, then electron mobility is improved, but the manufacturing process complexity increases
Solution Approach 1:
The gate structure is segmented into multiple distinct layers: the high-k gate insulation layer, the etch stop layer, and the metal gate electrode layer. This segmentation allows each layer to perform its specific function independently, with the etch stop layer specifically addressing the Fermi-level pinning issue while the metal layer provides the desired electrical characteristics, thereby managing manufacturing complexity through structured division.
3Stability of the object's composition
If the etch stop layer thickness is reduced to less than 20 Å to minimize its impact, then the gate structure integrity is maintained, but the etching selectivity becomes more difficult to control
Solution Approach 1:
The thickness of the etch stop layer is precisely controlled within a specific range (less than 20 Å) to optimize both structure integrity and etching selectivity. By adjusting this critical parameter, the patent achieves a balance where the etch stop layer is thin enough to maintain gate structure integrity but thick enough to provide adequate etching selectivity and prevent direct contact between polysilicon and high-k material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with improved electrical performance by minimizing the Fermi-level pinning effect and maintaining the integrity of the gate insulation layer, leading to better transistor performance.
Implementation Method 1
when a gate electrode including polysilicon is formed directly on the gate insulation layer including the high-k material, the transistor may have an increased threshold voltage and decreased electron mobility due to the Fermi-level pinning effect
Implementation Method 2
The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern
Implementation Method 3
the hard mask layer may be patterned by performing a first wet etching process using an etching solution including ammonia water
Implementation Method 4
the hard mask layer may be patterned by further performing a second wet etching process using an etching solution including hydrogen fluoride, before performing the first wet etching process
Data Source
AI summary
There is provided a method of manufacturing a semiconductor device. In the method, a gate insulation layer including a high-k dielectric material is formed on a substrate. An etch stop layer is formed on the gate insulation layer. A metal layer is formed on the etch stop layer. A hard mask including amorphous silicon is formed on the metal layer. The metal layer is patterned using the hard mask as an etching mask to form a metal layer pattern.