3D Amorphous Silicon MAS Memory Cell Scaling
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Solution Overview
Problem
Current memory cell structures face challenges in scaling down memory cell size without reducing memory capacitance per unit area, limiting the development of high-density memory devices, and existing techniques are inadequate for achieving small geometric sizes and high reliability.
Innovation Solution
A three-dimensional (3D) amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure is developed, featuring a p-i-n diode junction and a thin-film-transistor (TFT) access device, with a high-k aluminum oxide layer for charge trapping, allowing for improved scaling properties and integration in a cross-point memory architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell size is reduced to increase circuit density, then more devices can be fabricated on each wafer, but memory capacitance per unit area is reduced
Solution Approach 1:
The patent transitions from planar 2D memory cell structures to three-dimensional vertically stacked structures. Multiple memory cells are stacked vertically along the z-axis, enabling increased storage density without reducing the lateral footprint of individual cells. This vertical stacking allows more memory cells to be packed on each wafer while maintaining sufficient capacitance through optimized vertical charge storage regions.
Solution Approach 2:
The patent implements nested structures where control gates, charge storage regions, and tunnel barriers are arranged in concentric or layered configurations. The control gates wrap around or overlay the charge storage regions, creating nested functional units that maximize space utilization while maintaining electrical isolation and functional integrity.
2Ease of manufacture
If conventional memory cell structures are used, then manufacturing processes are well-established, but scaling down is limited by process constraints
Solution Approach 1:
The patent modifies key structural parameters including transitioning to amorphous silicon materials, adjusting layer thicknesses in the vertically stacked structure, and changing the geometric configuration to three-dimensional stacked arrangements. These parameter changes enable scaling to smaller feature sizes while maintaining compatibility with modified conventional manufacturing processes.
Solution Approach 2:
The patent employs composite material structures combining amorphous silicon with other materials in multi-layer stacks. The vertically stacked memory cells utilize composite layers including tunnel barriers, charge storage regions, and control gates made from different materials optimized for their specific functions, enabling improved scaling properties while maintaining manufacturability.
3Productivity
If three-dimensional integration is implemented, then storage density is increased, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent divides the memory device into segmented vertically stacked units, each containing distinct functional layers (tunnel barrier, charge storage region, control gates). This segmentation allows independent optimization of each layer while maintaining overall system functionality, and enables modular manufacturing approaches where layers can be formed sequentially using standard deposition and patterning processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-density memory devices with improved signal-to-noise ratio, reduced scaling limitations, and compatibility with conventional CMOS technology, facilitating 3D integration and efficient charge storage with reduced access time and thermal budget constraints.
Implementation Method 1
an aluminum oxide layer on the p-type a-Si layer and at least one control gate overlying the aluminum oxide layer
Data Source
AI summary
A semiconductor device with an amorphous silicon (a-Si) metal-aluminum oxide-semiconductor (MAS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an aluminum oxide charge trapping layer on the a-Si p-i-n diode junction and a metal control gate overlying the aluminum oxide layer. A method is provided for making the a-Si MAS memory cell structure and can be repeated to integrate the structure three-dimensionally.