Amorphous Silicon Oxidation Barrier for Memory Word Line Interference
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Solution Overview
Problem
Memory devices face challenges with neighboring word line interference due to fringing electric fields, which lead to widened threshold voltage distributions and inaccurate programming, especially as devices are scaled down.
Innovation Solution
The solution involves reducing fringing electric fields by avoiding rounding of control gate layers during fabrication, achieved by depositing an amorphous silicon layer along the sidewalls of memory holes and oxidizing it to form a blocking oxide layer, which acts as an oxidation barrier for the sacrificial material of the control gate layers, and optionally recessing the control gate layers to increase the distance between the control gate and the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control gate layers are formed using conventional fabrication processes, then the manufacturing process is simple, but fringing electric fields cause neighboring word line interference and widened threshold voltage distributions
Solution Approach 1:
An amorphous silicon layer is deposited along the sidewalls of memory holes before forming the control gate layers. This preliminary layer serves as an oxidation barrier that prevents fringing electric fields from causing neighboring word line interference, thereby improving programming accuracy while managing fabrication complexity through a straightforward additional deposition step
Solution Approach 2:
The amorphous silicon layer acts as an intermediary barrier between the control gate layers and the surrounding environment. This intermediate layer blocks the harmful fringing electric fields without interfering with the normal operation of the control gates, resolving the contradiction between reliability and device complexity
2Quantity of substance
If device dimensions are scaled down to increase density, then storage capacity improves, but fringing electric fields become more significant and cause interference
Solution Approach 1:
The fringing electric fields that cause harmful interference at scaled dimensions are blocked by the amorphous silicon layer. This converts the harmful effect of scaling into a benefit by demonstrating that the same scaling, when combined with the barrier layer, achieves high density without the usual interference problems
Solution Approach 2:
The amorphous silicon layer is selectively applied along the sidewalls of memory holes in the regions where fringing electric fields are most problematic. This localized approach addresses the harmful effects of scaling precisely where they occur, allowing overall device density to improve while interference is suppressed at critical locations
3Reliability
If control gate layers are recessed to increase distance from channel region, then short-channel effects are reduced, but fabrication process becomes more complex
Solution Approach 1:
The amorphous silicon barrier layer is deposited in advance, before the control gate layers are formed and before any recessing operations. This preliminary action establishes the protective barrier that reduces short-channel effects, and the subsequent recessing process becomes simpler because the barrier layer is already in place and can guide the recess formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces neighboring word line interference, improving programming accuracy and reducing short-channel effects, resulting in narrower threshold voltage distributions and enhanced memory device performance.
Implementation Method 1
oxidizing the amorphous silicon layer to provide an oxidized silicon layer
Data Source
AI summary
Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, rounding off of the control gate layers due to inadvertent oxidation during fabrication is avoided. An amorphous silicon layer is deposited along the sidewall of the memory holes, adjacent to the control gate layers. Si3N4 is deposited along the amorphous silicon layer and oxidized in the memory hole to form SiO2. The amorphous silicon layer acts as an oxidation barrier for the sacrificial material of the control gate layers. The amorphous silicon layer is subsequently oxidized to also form SiO2. The two SiO2 layers together form a blocking oxide layer.