Amorphous Silicon MONOS Memory Cell with 3D Integration
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Solution Overview
Problem
Current memory cell structures face challenges in scaling down without reducing memory capacitance per unit area, limiting the development of high-density memory devices, and existing techniques are inadequate for achieving small geometry and low leakage current while being compatible with conventional CMOS processes.
Innovation Solution
The development of an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with a one-time programmable (OTP) function, featuring a p-i-n diode junction and a simple layered charge trapping element, allowing for three-dimensional integration and easy integration with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional memory cell structures are scaled down to increase circuit density, then more devices can be fabricated on each wafer, but the memory capacitance per unit area is reduced
Solution Approach 1:
The patent transitions from planar 2D memory cell structures to three-dimensional vertically-stacked configurations. Multiple memory cells are stacked vertically along the channel direction, with source and drain regions positioned at different vertical levels. This vertical stacking enables increased memory capacitance per unit area while maintaining small footprint dimensions, directly resolving the contradiction between circuit density and memory capacitance.
2Productivity
If device geometry is reduced to increase the number of devices per wafer, then fabrication throughput increases, but manufacturing precision requirements become more challenging
Solution Approach 1:
The memory cell structure is segmented into distinct functional layers including bottom plate, tunnel oxide, charge trapping layer, blocking oxide, and top plate, with source and drain regions separated vertically. This segmentation into discrete layers with defined interfaces simplifies the manufacturing process and enables better control over each component's dimensions and properties, reducing the overall manufacturing precision challenges despite small device geometry.
3Length of moving object
If conventional techniques are used to reduce memory cell size, then device dimensions decrease, but leakage current increases
Solution Approach 1:
The patent employs a composite dielectric structure consisting of tunnel oxide, charge trapping layer (such as nitride or aluminum oxide), and blocking oxide layers. This composite material architecture provides effective charge confinement and blocking capabilities, preventing leakage current while enabling small device dimensions. The multiple layers work synergistically to maintain electrical isolation and prevent unwanted current flow despite reduced cell size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables high reliability, small geometric cell size, low thermal budget for fabrication, and efficient data storage with improved signal-to-noise ratio, while being compatible with conventional CMOS processes and meeting stackability and thermal budget constraints for 3D memory cell structures.
Implementation Method 1
applying a predetermined voltage to form a conductive path through the amorphous silicon p-i-n diode junction
Implementation Method 2
aluminum oxide layer for charge trapping
Data Source
AI summary
A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-silicon (MONOS) or metal-aluminum oxide-silicon (MAS) memory cell structure with one-time programmable (OTP) function. The device includes a substrate, a first dielectric layer overlying the substrate, and one or more source or drain regions embedded in the first dielectric layer with a co-planar surface of n-type a-Si and the first dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes a second dielectric layer on the a-Si p-i-n diode junction and a metal control gate overlying the second dielectric layer. Optionally the device with OTP function includes a conductive path formed between n-type a-Si layer and the metal control gate. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.