Amorphous Silicon Resistive Memory Cell for Non-Volatile Capacitor

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Solution Overview

Problem

Current resistive memory cells face challenges in retention time due to limited defect sites in the amorphous silicon switching layer, leading to unpredictable switching behavior and reduced endurance, which affects the reliability of non-volatile memory devices.

Innovation Solution

Integrating a resistive memory cell with a transistor or capacitor, utilizing an amorphous silicon switching layer with a higher defect density to enhance retention time and programmability, allowing the device to switch between resistive states with controlled resistance values, thereby improving the endurance and predictability of the memory device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If amorphous silicon switching layer with limited defect sites is used, then device simplicity is maintained, but retention time and reliability deteriorate

Engineering Contradiction:

Improveretention timeVSAvoiddefect site density

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the physical and chemical parameters of the switching layer by using amorphous silicon with intentionally increased defect density, transforming the previously limiting factor into a functional advantage for enhancing retention time and switching reliability

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent creates a composite structure by integrating the resistive memory cell with a capacitor, forming a hybrid device that combines the non-volatile storage capability of the resistive cell with the charge retention capability of the capacitor, thereby improving overall reliability

Inventive Principle:

Principle #40Composite materials

2Duration of action of stationary object

If resistive memory cell is integrated with capacitor, then retention time is improved, but device complexity increases

Engineering Contradiction:

Improveretention timeVSAvoiddevice structure

Core Design Contradiction:

Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

The patent merges a resistive memory cell and a capacitor into a single integrated device, where the capacitor is connected to the resistive memory cell to form a combined structure that leverages both components' strengths for enhanced non-volatile storage

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The integrated device performs multiple functions: the resistive memory cell provides non-volatile data storage through resistance switching, while the capacitor maintains charge retention, creating a multi-functional device that addresses both storage and retention requirements

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If amorphous silicon with higher defect density is used, then programmability is improved, but manufacturing precision requirements increase

Engineering Contradiction:

ImproveprogrammabilityVSAvoiddefect density control

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent deliberately changes the defect density parameter of the amorphous silicon layer to a higher level, transforming it from a manufacturing defect into a controllable design parameter that enhances programmability and switching behavior

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The integration of a resistive memory cell with a transistor or capacitor in a non-volatile device using an amorphous silicon switching layer with increased defect density enhances retention time and programmability, improving the reliability and scalability of ultra-high density non-volatile memory devices by maintaining programmed capacitance values for extended periods.

Implementation Method 1

voltage-induced diffusion of metal ions into the silicon leads to the formation of conductive filaments

Methodology Applied

Scientific EffectIon diffusion: Diffusion

Implementation Method 2

Joule heating and electrochemical processes in binary oxides (e.g. NiO and TiO2)

Methodology Applied

Scientific EffectJoule heating: Joule Heating

Implementation Method 3

field assisted diffusion of ions in TiO2 and amorphous silicon (a-Si) films

Methodology Applied

Scientific EffectField assisted diffusion: Diffusion

Data Source

PatentUS8988927B2Non-volatile variable capacitive device including resistive memory cell

Publication Date: 2015.03.24 CROSSBAR INC

AI summary

A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device.