Amorphous Silicon Spacer Line Edge Roughness Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing spacer defined multiple patterning techniques in semiconductor manufacturing often result in rough edges of free-standing spacers, leading to poor quality patterning due to the crystallization of silicon layers during high-temperature processes, which causes line edge roughness in subsequent etching steps.
Innovation Solution
Incorporating an anti-crystallization dopant in the lower amorphous silicon layer to maintain its amorphous state during the formation of an upper hard mask layer and subsequent etching processes, thereby reducing line edge roughness by preventing crystallization and ensuring smooth sidewall formation of spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the silicon layer is kept amorphous during high-temperature processing, then line edge roughness is reduced, but the structural stability may be compromised
Solution Approach 1:
The patent creates a composite structure consisting of multiple layers including the amorphous silicon layer, hard mask layers, and potentially other functional layers. This composite structure provides the necessary structural stability and mechanical support, allowing the amorphous silicon layer to maintain its smooth, non-crystalline state even during high-temperature processing without compromising overall structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces line edge roughness and enhances the quality of patterning by maintaining the amorphous state of the silicon layer, resulting in highly uniform and smooth spacer features that can be used for precise etching and patterning of underlying materials.
Implementation Method 1
providing a lower amorphous silicon layer on the substrate, wherein the lower amorphous silicon layer is provided with an anti-crystallization dopant
Implementation Method 2
forming an upper hard mask layer above the lower amorphous silicon layer by a method comprising heating the substrate to a temperature above 550° C.
Data Source
AI summary
The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.