Amorphous Silicon Stop Layer for Metal Gate Etch Protection
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Solution Overview
Problem
In the semiconductor industry, polysilicon gates face issues such as boron penetration and depletion effects, leading to reduced gate capacitance and performance in high-k metal gate transistors, and voids formed during work function metal deposition affect device performance.
Innovation Solution
A method involving a substrate with defined regions, forming a high-k dielectric layer, a first bottom barrier metal layer, a stop layer of amorphous silicon, and subsequent metal layers to prevent etchant exposure and maintain the thickness of the first BBM layer, ensuring effective fabrication of semiconductor devices with multi-VT gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon is used as gate electrode material, then the fabrication process is simplified, but boron penetration and depletion effects occur leading to reduced gate capacitance and performance
Solution Approach 1:
The patent extracts polysilicon from the gate electrode structure and replaces it with metal layers (tungsten, cobalt, or copper) combined with high-k dielectric materials. This removal of polysilicon eliminates the boron penetration and depletion effects while maintaining fabrication feasibility through alternative material systems.
Solution Approach 2:
The patent employs composite material structures combining metal layers (for work function control) with high-k dielectric materials (for enhanced gate capacitance). This composite approach achieves both improved electrical performance and compatibility with existing fabrication processes.
2Reliability
If work function metal layer is deposited for multi-VT devices, then device performance is improved, but voids are formed during deposition affecting performance
Solution Approach 1:
The patent introduces a stop layer as an intermediary material between the high-k dielectric layer and the work function metal layer. This stop layer serves as a deposition barrier that prevents void formation while allowing the work function metal to be properly deposited, thus maintaining manufacturing precision.
Solution Approach 2:
The stop layer is formed in advance before the work function metal deposition process. This preliminary action prepares the surface and establishes a controlled interface that prevents void formation during subsequent metal layer deposition, ensuring manufacturing precision is maintained.
3Productivity
If etching process is performed without stop layer protection, then fabrication progress is made, but first BBM layer is exposed to etchant causing thickness variation
Solution Approach 1:
The stop layer acts as a protective intermediary during etching processes. It allows etching to proceed for fabrication progress while preventing the etchant from reaching and damaging the first BBM layer, thus maintaining manufacturing precision of the BBM layer thickness.
Solution Approach 2:
The stop layer is positioned beforehand to cushion and protect the first BBM layer from etchant exposure. This prior protective measure ensures that while etching can proceed for fabrication progress, the BBM layer thickness remains precise and unaffected.
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first region and a second region; forming a high-k dielectric layer on the first region and the second region; forming a first bottom barrier metal (BBM) layer on the high-k dielectric layer of the first region and the second region; forming a stop layer on the first region and the second region; removing the stop layer on the second region; and forming a second BBM layer on the first region and the second region.