Amorphous Silicon TFT Contact Doping for Low-Leakage Switching

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Solution Overview

Problem

Existing thin-film transistors (TFTs) face poor ohmic contact performance between the amorphous silicon semiconductor layer and the source-drain electrodes, leading to low on-state current and high off-state current, which hinders integration of low temperature poly-silicon and amorphous silicon TFT production lines.

Innovation Solution

Doping ions, particularly phosphorus ions, into the amorphous silicon semiconductor layer through an ion implantation process to create a high concentration (≥5*10^20 atoms/cc) near the source and drain electrodes, followed by a controlled wet etching process to form distinct contact and channel regions, ensuring great ohmic contact and reduced leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If ion implantation is performed to increase ion concentration in the surface region, then ohmic contact performance and on-state current are improved, but manufacturing complexity increases

Engineering Contradiction:
Improveohmic contact performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The ion implantation process is performed on the amorphous silicon semiconductor layer before the source and drain electrodes are formed. This preliminary doping action ensures that the high ion concentration region is already in place when the electrodes are deposited, eliminating the need for subsequent complex re-doping processes and simplifying the overall manufacturing sequence

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The ion implantation is selectively applied to create a localized high ion concentration region specifically in the surface area where the source and drain electrodes will contact the semiconductor layer. This localized doping approach improves ohmic contact performance at the critical contact regions without requiring uniform doping throughout the entire device structure

Inventive Principle:
Principle #3Local quality

2Power

If ion concentration in the surface region is increased to improve on-state current, then switching characteristics are enhanced, but leakage current may increase

Engineering Contradiction:
Improveon-state currentVSAvoidleakage current
Core Design Contradiction:
PowerVSObject-generated harmful factors

Solution Approach 1:

The ion implantation process creates a localized high ion concentration region confined to the surface area where the source and drain electrodes contact the semiconductor layer. The ion concentration decreases with depth and remains low in the channel region, ensuring high on-state current at the contacts while maintaining low leakage current in the active channel

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The amorphous silicon semiconductor layer is functionally segmented into different regions with different ion concentrations: a high ion concentration surface region for ohmic contact (≥5×10^20 atoms/cc) and a low ion concentration channel region for current control. This segmentation allows independent optimization of contact performance and switching characteristics

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the on-state current and reduces the off-state current, resulting in a high on-to-off current ratio and improved switching characteristics of the amorphous silicon thin-film transistor.

Implementation Method 1

ions doped by an ion implantation process are present in a region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS12610581B2Amorphous silicon thin-film transistor, method for preparing same, and display panel
Publication Date: 2026.04.21 ORDOS YUANSHENG OPTOELECTRONICS
  • US12610581B2 patent drawing
  • US12610581B2 patent drawing
  • US12610581B2 patent drawing

AI summary

Provided is an amorphous silicon thin-film transistor including an amorphous silicon semiconductor layer, a source electrode, and a drain electrode that are successively disposed on a base substrate. Ions doped by an ion implantation process are present in a region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer. A concentration of the ions in a surface region, proximal to the source electrode and the drain electrode, of the amorphous silicon semiconductor layer is greater than or equal to 5*10{circumflex over ( )}20 atoms/cc.