Amorphous Silicon TFT Electrode Protection
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Solution Overview
Problem
In the reverse manufacturing method for amorphous silicon thin film transistors, the exposure of the second electrode metal layer during dry etching leads to surface damage from plasma gases, affecting device performance and transmittance.
Innovation Solution
A protective insulating layer, typically silicon nitride with a thickness of 500 to 1000 angstroms, is used to cover the source/drain electrode layer, which is etched with cupric acid to ensure flushness with the channel, preventing damage from plasma gases during dry etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the photoresist material is removed first and then channel etching is performed (reverse manufacturing method), then the N+ doped layer can be completely removed and device width can be reduced, but the second electrode metal layer is completely exposed and damaged by plasma gas during dry etching
Solution Approach 1:
A protective insulating layer is introduced as an intermediary between the electrode layer and the plasma gas during dry etching. This protective layer prevents direct contact between the harmful plasma gas and the electrode layer, thereby eliminating surface damage while maintaining the advantages of the reverse manufacturing method.
Solution Approach 2:
The protective insulating layer is formed on the electrode layer before the dry etching process begins. This preliminary protective action ensures that the electrode layer is shielded from plasma gas damage throughout the subsequent etching process, allowing complete removal of the N+ doped layer without compromising electrode integrity.
2Productivity
If the second electrode metal layer is completely exposed during dry etching, then channel etching can be performed, but the surface of the electrode layer is damaged and discolored
Solution Approach 1:
The protective insulating layer serves as a mediator that allows the dry etching process to proceed efficiently while preventing direct damage to the electrode layer. The plasma gas etches through the protective layer without causing surface damage or discoloration to the underlying electrode material.
Solution Approach 2:
The protective insulating layer provides localized protection specifically where needed - on the electrode layer surface exposed during dry etching. This localized quality enhancement allows high-speed etching in the channel region while protecting the electrode layer from plasma gas damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution prevents surface damage to the electrode layer, ensuring consistent device performance, simplifying the manufacturing process, and achieving high transmittance without affecting subsequent processes.
Implementation Method 1
The protective insulating layer is etched with cupric acid to make the protective insulating layer and the source/drain electrode layer flush with each other in the channel
Implementation Method 2
when the active layer is dry-etched to form the channel, a second electrode metal layer (usually made of copper or aluminum) is completely exposed, which causing a surface of the second electrode metal layer to be damaged by a plasma gas under an electric field
Data Source
AI summary
The present invention provides an amorphous silicon thin film transistor and a manufacturing method of the amorphous silicon thin film transistor, which comprise: a substrate, a gate electrode layer, a gate insulating layer, an active layer, a source/drain electrode layer, an N+-doped layer, a protective insulating layer, and a passivation layer. The N+-doped layer is disposed between the active layer and the source/drain electrode layer. The protective insulating layer is disposed on the source/drain electrode layer. A channel is formed in the source/drain electrode layer and penetrates the N+-doped layer and the protective insulating layer. The passivation layer covers the channel and the protective insulating layer. The protective insulating layer and the source/drain electrode layer are flush with each other in the channel.