Amorphous Silicon TFT Threshold Voltage Offset Reduction
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Solution Overview
Problem
The Gate Driven on Array (GOA) technology for display panels faces quality and reliability risks due to threshold voltage offset in thin film transistors (TFTs) caused by doping characteristics of amorphous silicon semiconductor, affecting display performance.
Innovation Solution
A method for manufacturing a thin film transistor structure that involves depositing and patterning metal layers, insulation layers, and doped layers, followed by specific heating processes in nitrogen and ammonia atmospheres to reduce threshold voltage offset and enhance channel region stability, using techniques like radio frequency magnetron sputtering and plasma enhanced chemical vapor deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GOA technology is used to integrate gate drive circuit on array substrate, then product costs are reduced by omitting gate drive integrated circuit, but threshold voltage offset in TFT devices causes quality and reliability risks
Solution Approach 1:
The patent applies parameter changes by modifying the heating treatment parameters of the channel region. Specifically, it uses a two-stage heating process: first heating in nitrogen atmosphere at 250-350°C for 1-10 minutes to reduce weak bonds, then heating in ammonia atmosphere at 250-350°C for 1-10 minutes to passivate dangling bonds. These parameter changes effectively reduce threshold voltage offset while maintaining the cost benefits of GOA technology.
Solution Approach 2:
The patent uses inert and reactive gas atmospheres (nitrogen and ammonia) during heating treatment to protect the channel region from oxidation and to facilitate bond recovery and passivation. The nitrogen atmosphere provides an inert environment for initial heating, while the ammonia atmosphere provides a reactive environment for passivating dangling bonds, thereby reducing threshold voltage offset without adding complex manufacturing steps.
2Ease of operation
If amorphous silicon semiconductor is doped in switch element, then scanning function is achieved, but threshold voltage offset occurs affecting display performance
Solution Approach 1:
The patent applies preliminary action by performing heating treatment on the channel region before the TFT device is fully assembled and tested. The two-stage heating process (nitrogen atmosphere followed by ammonia atmosphere) is conducted early in the manufacturing process to prevent weak bond formation and dangling bonds, thereby preemptively reducing threshold voltage offset before it can affect display performance.
Solution Approach 2:
The patent modifies the physical and chemical parameters of the channel region through controlled heating treatment. By changing the temperature (250-350°C), time (1-10 minutes), and atmospheric composition (nitrogen and ammonia), the patent recovers weak bonds and passivates dangling bonds in the amorphous silicon channel, thereby improving threshold voltage control precision while maintaining the scanning function.
3Reliability
If channel region is heated in ammonia atmosphere only, then dangling bonds are passivated, but weak bonds remain affecting threshold voltage stability
Solution Approach 1:
The patent segments the heating treatment process into two distinct stages: first heating in nitrogen atmosphere to address weak bonds, then heating in ammonia atmosphere to passivate dangling bonds. This segmentation allows each heating stage to target specific types of bonds, thereby comprehensively improving threshold voltage stability while keeping each individual heating step relatively simple and controllable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces threshold voltage drift and improves display performance by reducing weak bonds in amorphous silicon and enhancing irradiation stability, leading to better image quality and reliability in display devices.
Implementation Method 1
placing the channel region in a preset gas atmosphere for heating processing, the channel region is first heated for a first preset time, then placed in an atmosphere of nitrogen to heat for a second preset time, and at last placed in an atmosphere of ammonia to heat for a third preset time
Implementation Method 2
depositing a first metal layer on the substrate
Implementation Method 3
depositing a gate insulation layer on the substrate
Data Source
AI summary
Provided are a thin film transistor structure, a manufacturing method thereof, and a display device. The method comprises: providing a substrate (10), and sequentially forming a gate (20), a gate insulating layer (30), an active layer (40), a doped layer (50), a source (610), a drain (620) and a channel region (70) on the substrate (10); placing the channel region (70) in a preset gas atmosphere for heating treatment; wherein, the channel region (70) is placed in a nitrogen atmosphere to heat for a first preset time, in a mixed atmosphere of nitrogen and ammonia to heat for a second preset time, in an ammonia atmosphere to heat for a third preset time; or first heating the channel region (70) for a fourth preset time, finally placing in the ammonia atmosphere to heat for a fifth preset time.