Amorphous Silicon Thickness Gradient for Polysilicon Grain Control
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Solution Overview
Problem
Conventional methods for manufacturing AMOLED display devices fail to simultaneously meet the requirements of high electron mobility in peripheral circuit areas and low leakage current in display areas due to uniform poly-silicon grain sizes in low temperature poly-silicon thin film transistors.
Innovation Solution
A method involving the formation of amorphous silicon layers with different thicknesses in display and peripheral circuit areas, followed by excimer laser annealing to create poly-silicon layers with varying grain sizes, where the thinner layer in the display area forms a poly-silicon layer with smaller grain size for low leakage current and the thicker layer in the peripheral circuit area forms a poly-silicon layer with larger grain size for high electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform thickness amorphous silicon layer is used in both display area and peripheral circuit area, then manufacturing process is simple, but cannot simultaneously achieve low leakage current in display area and high electron mobility in peripheral circuit area
Solution Approach 1:
The patent applies local quality by forming amorphous silicon layers with different thicknesses in different regions: a first amorphous silicon layer with first thickness in the display area and a second amorphous silicon layer with second thickness in the peripheral circuit area. This regional differentiation enables the display area transistors to achieve low leakage current while peripheral circuit area transistors achieve high electron mobility, resolving the contradiction between manufacturing simplicity and transistor performance.
Solution Approach 2:
The patent segments the amorphous silicon layer into two distinct layers with different thicknesses based on functional requirements. The first amorphous silicon layer is formed in the display area with a thickness optimized for low leakage current, while the second amorphous silicon layer is formed in the peripheral circuit area with a thickness optimized for high electron mobility. This segmentation allows each region to be optimized independently while using the same excimer laser annealing process.
2Reliability
If different thickness amorphous silicon layers are formed in display and peripheral circuit areas, then can simultaneously achieve low leakage current and high electron mobility, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the formation of different thickness amorphous silicon layers into a single excimer laser annealing process. By using a patterned mask during the annealing process, the first and second amorphous silicon layers are formed with different thicknesses in one step, rather than requiring separate deposition and processing steps. This merging approach reduces manufacturing process complexity while achieving the desired different thickness configuration.
Solution Approach 2:
The patent utilizes parameter changes in the excimer laser annealing process to achieve different amorphous silicon layer thicknesses. By controlling the laser energy distribution and mask pattern, the annealing process selectively forms the first amorphous silicon layer with first thickness and the second amorphous silicon layer with second thickness from the same amorphous silicon film, simplifying the manufacturing process while achieving the required thickness variation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the simultaneous satisfaction of high electron mobility in peripheral circuit transistors and low leakage current in display area transistors, enhancing the performance of thin film transistors in AMOLED devices.
Implementation Method 1
processing the first amorphous silicon layer and the second amorphous silicon layer simultaneously by an excimer laser annealing to form a first poly-silicon layer located in the display area and a second poly-silicon layer located in the peripheral circuit area
Implementation Method 2
processing the first amorphous silicon layer and the second amorphous silicon layer simultaneously by an excimer laser annealing to form a first poly-silicon layer
Implementation Method 3
processing the first amorphous silicon layer and the second amorphous silicon layer simultaneously by an excimer laser annealing
Data Source
AI summary
An array substrate and manufacturing method thereof, a display panel and a display device are provided. The array substrate includes a display area and a peripheral circuit area. The method includes forming an amorphous silicon thin film on the base substrate, forming a first amorphous silicon layer in the display area and a second amorphous silicon layer in the peripheral circuit area by a patterning process, so that a thickness of the first amorphous silicon layer is less than a thickness of the second amorphous silicon layer; and processing the first amorphous silicon layer and the second amorphous silicon layer simultaneously by an excimer laser annealing to form a first poly-silicon layer in the display area and a second poly-silicon layer in the peripheral circuit area, a grain size of the first poly-silicon layer being less than a grain size of the second poly-silicon layer.