Amorphous Silicon UV Blocking Layer for Semiconductor Reliability
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Solution Overview
Problem
Conventional non-volatile memory semiconductor structures face issues with charge loss and UV light sensitivity due to the low etching rate of silicon rich oxide (SSRO and SRO) layers, leading to over or under etching of contact holes and residual material causing leakage problems.
Innovation Solution
A semiconductor structure is developed with an amorphous silicon layer as the UV blocking layer and silicon nitride as the electric leakage protection material, replacing SSRO/SRO, which is used in the dielectric layer and contact hole sidewalls to prevent leakage and improve etching control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If SSRO or SRO is used as UV blocking layer, then UV light blocking capability is improved, but etching rate becomes too low causing over etching or insufficient etching of contact holes
Solution Approach 1:
The patent divides the dielectric layer into multiple layers with different functions: the first dielectric layer (SSRO/SRO) serves as UV blocking layer, while the second dielectric layer (silicon oxide) has higher etching rate for precise contact hole formation. This segmentation allows each layer to optimize its specific function without compromising the other.
Solution Approach 2:
The patent changes the material composition parameter of the dielectric layers, using SSRO/SRO with high silicon content for UV blocking in the first layer, and silicon oxide with lower silicon content for better etching characteristics in the second layer. This parameter differentiation resolves the contradiction between UV blocking and etching precision.
2Object-affected harmful factors
If SSRO or SRO is used as UV blocking layer, then UV light blocking capability is improved, but residual material remains in dead space causing punch through effect
Solution Approach 1:
The patent segments the dielectric structure into two layers where the second dielectric layer (silicon oxide) with higher etching rate completely fills and etches the dead space regions, preventing residual SSRO/SRO material from remaining. This ensures no punch through effects occur while the first layer maintains UV blocking function.
Solution Approach 2:
The second dielectric layer acts as an intermediary material that facilitates complete etching of contact holes and dead spaces. Its higher etching rate allows it to clear residual material that the first SSRO/SRO layer cannot be fully removed, thereby preventing punch through effects.
3Device complexity
If conventional interlayer dielectric structure is used, then manufacturing simplicity is maintained, but electricity leakage occurs at gate top surface or between gate and substrate
Solution Approach 1:
The patent introduces an additional second dielectric layer between the first dielectric layer and the gate structure. This segmentation creates an extra insulation barrier that effectively prevents electricity leakage at the gate top surface and between gate and substrate, while maintaining overall structural organization.
Solution Approach 2:
The patent uses a composite dielectric structure combining SSRO/SRO (first dielectric layer) with silicon oxide (second dielectric layer). This composite approach leverages the UV blocking capability of SSRO/SRO and the superior insulation properties of silicon oxide to simultaneously achieve both UV protection and leakage prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents charge loss and UV light penetration, enhancing the etching process precision and eliminating residual material issues, thereby improving the reliability of non-volatile memory devices.
Implementation Method 1
forming a dielectric layer on the conductive layer, wherein the dielectric layer comprises at least an amorphous silicon layer... a novel UV blocking layer which can solve aforementioned problems
Implementation Method 2
The electric leakage protection material is positioned in the dielectric layer and the sidewall of the contact hole. In this way, the sidewall of the contact hole is surrounded by the electric leakage protection material and current leakage can be controlled.
Data Source
AI summary
A semiconductor device is provided. An amorphous silicon layer that acts as a UV blocking layer replaces a conventional silicon-rich oxide (SRO) layer or the super silicon-rich oxide (SSRO) layer. By doing this, the process window is increased. In addition, silicon nitride sidewall spacer is formed inside the contact hole to prevent charge loss.