Amorphous Titanium Barrier for Dual Poly Gate Transistors
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Solution Overview
Problem
Dual CMOS transistors face limitations due to boron penetration and gate depletion in PMOS transistors, leading to increased surface resistance and signal delay, particularly when using tungsten silicide/tungsten nitride barrier layers, which react with boron and fail to serve as effective barriers, causing electrode agglomeration and performance degradation.
Innovation Solution
Incorporating an amorphous titanium layer as a barrier between the lower and upper gate electrodes in both NMOS and PMOS regions to improve interface properties and reduce surface resistance, with a tungsten nitride or tungsten layer serving as the upper gate electrode, thereby preventing boron diffusion and maintaining electrode functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a tungsten silicide/tungsten nitride barrier layer is used, then the upper gate electrode can be formed, but the barrier layer reacts with boron causing increased surface resistance and signal delay
Solution Approach 1:
An amorphous silicon layer is introduced as an intermediary barrier between the tungsten silicide/tungsten nitride layer and the boron-doped polysilicon lower gate electrode. This intermediate layer prevents direct contact and reaction between the barrier layer and boron, eliminating the formation of high-resistance boron nitride while maintaining the electrode barrier functionality.
Solution Approach 2:
The barrier structure is designed as a composite multi-layer system combining tungsten silicide, tungsten nitride, and amorphous silicon layers. Each material contributes specific properties: tungsten silicide provides barrier functionality, tungsten nitride enhances stability, and amorphous silicon prevents boron diffusion, creating a synergistic composite structure that resolves the contradiction.
2Reliability
If the barrier layer is formed with a stacked structure including tungsten silicide/tungsten nitride, then the upper gate electrode can be formed, but the lower gate electrode and tungsten silicide agglomerate degrading electrode function
Solution Approach 1:
The amorphous silicon layer serves as a stabilizing intermediary between the lower gate electrode and tungsten silicide layer, preventing direct interaction that would cause agglomeration. This intermediate barrier maintains the structural integrity and compositional stability of the electrode system throughout thermal processing.
Solution Approach 2:
The multi-layer composite structure with amorphous silicon provides enhanced structural stability by creating distinct interfaces that prevent material mixing and agglomeration. The composite design ensures each layer maintains its intended function without degradation from thermal exposure.
3Object-generated harmful factors
If a Ti/WN stacked barrier layer is used, then boron diffusion is interrupted, but the word line resistance increases due to small grain size
Solution Approach 1:
A thin amorphous silicon layer is used as a disposable, sacrificial barrier that effectively blocks boron diffusion during processing but does not significantly impact the electrical properties of the final structure. This thin layer provides the necessary barrier function without introducing the grain size limitations of titanium-based structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The amorphous titanium layer effectively reduces surface resistance and prevents boron diffusion, enhancing the performance of dual poly gate transistors by maintaining the integrity of the lower and upper gate electrodes, thus improving device integration, yield, and PMOS properties.
Implementation Method 1
the amorphous titanium layer effectively reduces surface resistance and prevents boron diffusion
Implementation Method 2
a metal layer, such as a tungsten (W) layer, is formed as an upper gate electrode over a lower gate electrode to obtain a low word line resistance
Data Source
AI summary
A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, active regions of the semiconductor substrate defined by a device isolation structure formed in the semiconductor substrate, the active regions including an NMOS active region defined in the NMOS region and a PMOS active region defined in the PMOS region, a gate insulating film disposed over the active regions, and a dual poly gate including an amorphous titanium layer formed over the gate insulating film in the NMOS region and the PMOS region. The dual poly gate includes a stacked structure having a lower gate electrode formed of an impurity doped polysilicon layer, a barrier layer including the amorphous titanium layer, and an upper gate electrode formed of a tungsten layer.