Dual-Sided Amphi-FET Cell Layout for Dense 3D Routing
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Solution Overview
Problem
As technology nodes shrink, existing three-dimensional integrated circuits (3DICs), fin field effect transistors (FinFETs), gate all around (GAA) transistors, and backside routing structures struggle to maintain reduced device area and efficient routing options, leading to increased device size and power consumption.
Innovation Solution
The use of amphi-field effect transistors (amphi-FETs) with active devices formed on both sides of a substrate, connected through conductive elements extending through the substrate, allowing signal and power transfer without additional routing structures, and enabling mixed cell arrangements for increased gate density and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional 3DIC structures with devices formed on one side of substrate are used, then manufacturing process is simpler, but device area increases and routing efficiency decreases
Solution Approach 1:
The patent transitions from planar single-sided device formation to bi-directional formation on both sides of the substrate. Active devices are formed on both the front and back surfaces of the semiconductor substrate, utilizing the third dimension (substrate thickness) to increase functional density without expanding planar footprint. This dimensional transition enables doubled device capacity within the same area.
2Adaptability or versatility
If additional routing structures are added to connect devices, then routing options increase, but device area and power consumption increase
Solution Approach 1:
The patent creates symmetric routing structures on both sides of the substrate that mirror each other. Conductive interconnects and insulation layers are formed in corresponding patterns on the front and back surfaces, establishing parallel routing paths. This copying approach provides redundant routing options while maintaining balanced electrical characteristics and minimizing additional power consumption.
3Quantity of substance
If technology nodes continue to shrink, then device density increases, but routing efficiency decreases and device size increases
Solution Approach 1:
The patent divides the routing function into two separate sides of the substrate. Front-side devices connect to back-side devices through vertical conductive paths, segmenting the routing complexity into manageable layers. This segmentation allows independent optimization of front-side logic and back-side interconnect, maintaining routing efficiency as technology nodes shrink.
4Quantity of substance
If mixed cell arrangements are implemented, then gate density increases and device size reduces, but alignment complexity increases
Solution Approach 1:
The patent employs asymmetric cell arrangements where different cell types and configurations are strategically placed on front and back sides of the substrate. This asymmetric布局 allows optimization of each side for specific functions while maintaining overall system integration. The asymmetry enables higher gate density by eliminating wasted space from uniform positioning constraints.
Data Source
AI summary
A semiconductor device includes a substrate, a first cell having a first functionality, and a second cell having a second functionality. The first cell includes a first portion on a first side of the substrate, wherein the first portion includes a first conductive element; a second portion on a second side of the substrate, wherein the second portion includes a second conductive element; and a first conductive via extending through the substrate and electrically connecting the first conductive element to the second conductive element. The second cell includes a third portion on the first side of the substrate, wherein the third portion includes a third conductive element; a fourth portion on the second side of the substrate, wherein the fourth portion includes a fourth conductive element; and a second conductive via extending through the substrate and electrically connecting the third conductive element to the fourth conductive element.