Amphi-FET Structure With Through-Substrate S/D Connection
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Solution Overview
Problem
As technology nodes shrink, three-dimensional integrated circuits (3DICs), fin field effect transistors (FinFETs), gate all around (GAA) transistors, and backside routing structures struggle to maintain reduced device area and efficiency in signal transfer, leading to increased resistance and power consumption.
Innovation Solution
The implementation of amphi-field effect transistors (amphi-FETs), which feature active devices on both sides of a substrate, allowing for direct electrical connections through the substrate, reducing the need for additional routing and through-substrate via structures, thereby enhancing gate density and minimizing power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional 3DIC structures with TSV are used, then device stacking is achieved, but routing area is reduced and interconnect complexity increases
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by forming conductive interconnect structures that extend through the substrate in the vertical dimension. This allows signals to route above and below active devices, effectively utilizing the Z-axis for routing paths and thereby preserving planar area while enabling device stacking.
Solution Approach 2:
The patent segments the routing function across multiple layers and dimensions. Instead of confining all routing to a single planar layer, the interconnect structures are divided into multiple segments that route signals through different vertical levels, allowing parallel signal paths and reducing routing congestion in any single layer.
2Adaptability or versatility
If more routing options are provided, then routing flexibility increases, but device area increases
Solution Approach 1:
The patent resolves this contradiction by adding the vertical dimension to routing. Conductive interconnect structures extend through the substrate, providing multiple routing paths in the Z-direction. This three-dimensional routing capability increases routing flexibility without requiring additional planar area, as the extra routing options are achieved by utilizing the vertical space above and below the substrate plane.
3Productivity
If technology nodes shrink, then device density increases, but resistance and power consumption increase
Solution Approach 1:
The patent addresses the resistance and power consumption issues by creating three-dimensional interconnect structures that provide multiple parallel conduction paths. The conductive interconnects extend vertically through the substrate, forming multiple resistance pathways that can be parallelized, thereby reducing overall resistance and power consumption despite continued scaling to smaller technology nodes.
4Reliability
If through-substrate via structures are added, then electrical connections are improved, but device complexity and area increase
Solution Approach 1:
The patent merges the function of through-substrate vias with the existing conductive interconnect structures. Instead of adding separate via structures, the interconnects are formed to naturally extend through the substrate and make electrical connections, combining the routing and connection functions into a single integrated structure that reduces overall device complexity.
Data Source
AI summary
A method of making a semiconductor device includes forming a first active region on a first side of a substrate. The method further includes forming a first source/drain (S/D) electrode surrounding a first portion of the first active region. The method further includes forming an S/D connect via extending through the substrate. The method further includes flipping the substrate. The method further includes forming a second active region on a second side of the substrate, wherein the second side of the substrate is opposite to the first side of the substrate. The method further includes forming a second S/D electrode surrounding a first portion of the second active region, wherein the S/D connect directly contacts both the first S/D electrode and the second S/D electrode.