Asynchronous Multi-Plane Read Control for NAND Flash Memory

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Solution Overview

Problem

Existing NAND Flash memory devices perform multi-plane read operations synchronously, limiting system performance as the host cannot issue read instructions when the memory device is busy, restricting operation speed and efficiency.

Innovation Solution

Implementing an asynchronous multi-plane independent (AMPI) read operation architecture with a main microcontroller unit (MCU) and multiple AMPI read units, along with a multiplexing circuit to manage AMPI and non-AMPI read control signals, allowing independent control of each memory plane and enabling read operations even when the device is busy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If synchronous multi-plane read operation is used, then the memory device can perform read operations on multiple planes, but the host cannot issue read instructions when the memory device is busy, limiting operation speed and efficiency

Engineering Contradiction:
Improveoperation speedVSAvoidhost flexibility
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The memory device is divided into multiple independent planes (N memory planes), each capable of performing read operations independently. Each plane has its own read pipeline and control logic, allowing parallel read operations without blocking the host controller when one plane is busy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The asynchronous read operation architecture ensures continuous data flow from multiple planes to the host simultaneously. While one plane is being read, the host can already receive data from other planes or issue new read instructions, eliminating idle waiting time and maintaining continuous useful action.

Inventive Principle:
Principle #20Continuity of useful action

2Productivity

If asynchronous multi-plane independent read operation architecture is implemented, then the host can issue read instructions during busy states, improving operation speed and flexibility, but the number of control units increases

Engineering Contradiction:
Improvesystem performanceVSAvoidnumber of control units
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Multiple AMPI read units share common resources including the multiplexing circuit, voltage generation circuitry, and data output bus. This merging of shared resources reduces the overall number of control units needed compared to having completely independent control logic for each plane.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each AMPI read unit is designed as a universal module that can control read operations on any memory plane. The multiplexing circuit dynamically routes control signals from the appropriate AMPI read unit to the target plane, allowing one control unit to serve multiple functions across different planes.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If multiple AMPI read units are used to control multiple memory planes, then independent read operations can be performed, but power consumption increases

Engineering Contradiction:
Improveread operation efficiencyVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The AMPI read units and multiplexing circuit are activated only during read operations. During non-read periods or when specific planes are not being accessed, these control units can enter low-power or idle states, reducing overall power consumption while maintaining read operation efficiency when needed.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

Multiple AMPI read units share common power supply circuitry, voltage generation units, and data output interfaces. This sharing of power-consuming components reduces the total power consumption compared to having completely separate power systems for each control unit.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11763892B2Memory device and asynchronous multi-plane independent read operation thereof
Publication Date: 2023.09.19 YANGTZE MEMORY TECH CO LTD
  • US11763892B2 patent drawing
  • US11763892B2 patent drawing
  • US11763892B2 patent drawing

AI summary

In certain aspects, a method for operating a memory device is disclosed. The memory device includes a plurality of memory planes. Whether an instruction is an asynchronous multi-plane independent (AMPI) read instruction or a non-AMPI read instruction is determined. In response to the instruction being an AMPI read instruction, an AMPI read control signal is generated based on the AMPI read instruction, and the AMPI read control signal is directed to a corresponding memory plane of the memory planes. In response to the instruction being a non-AMPI read instruction, a non-AMPI read control signal is generated based on the non-AMPI read instruction, and the non-AMPI read control signal is directed to each memory plane of the memory planes.