Amplifier Circuit Feedback Layout for Shorter Settling Time
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Solution Overview
Problem
Existing amplifier circuits, such as the super source follower (SSF) circuit, suffer from large overshoot and undershoot in output waveforms, leading to longer rising and falling settling times.
Innovation Solution
The proposed amplifier circuit incorporates specific configurations of field-effect transistors with feedback loops and differential amplifiers to control current flow, including transistors of different conductivity types and fixed potentials, to stabilize output waveforms and reduce settling times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a super source follower (SSF) circuit is used to achieve low output impedance and large driving force, then the driving capability is improved, but large overshoot and undershoot occur in the output waveform leading to longer rising and falling settling times
Solution Approach 1:
The patent introduces a feedback transistor connected between the output terminal and the gate terminal of the first transistor. This feedback mechanism monitors the output voltage and adjusts the gate voltage accordingly, preventing excessive voltage swings that cause overshoot and undershoot. The feedback loop stabilizes the output waveform during transitions, reducing settling time while maintaining the strong driving capability provided by the SSF circuit configuration.
2Loss of time
If feedback transistors are added to reduce overshoot and undershoot, then the settling time is improved, but the device complexity increases
Solution Approach 1:
The patent merges the feedback function with the existing SSF circuit structure by integrating the feedback transistor into the gate control network. The feedback transistor shares the gate terminal with the first transistor and works in conjunction with the current source transistor, combining multiple functions (amplification, current sourcing, and feedback control) into a unified circuit architecture. This integration approach reduces the need for separate feedback components and minimizes overall circuit complexity.
Data Source
AI summary
In the amplifier circuit, the rising settling time and the falling settling time are kept short. The amplifier circuit includes a first transistor of a first conductivity type having a first control terminal; a second transistor of a second conductivity type different from the first conductivity type, the second transistor having a second control terminal connected to an input terminal and a fourth current terminal connected to the first control terminal; a third transistor; and a fourth transistor of a fourth conductivity type different from the first conductivity type, the fourth transistor having a fourth control terminal connected to the first control terminal at an equal potential, and a seventh current terminal connected to a third fixed potential.