High-Frequency Amplifier Gain Switching With IIP3 and Phase Control
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Solution Overview
Problem
High-frequency low noise amplifiers (LNAs) face challenges in achieving variable gain modes with defined reflection characteristics, noise figure, and Input 3rd-order Intercept Point (IIP3) specifications, particularly in ensuring IIP3 falls within allowable ranges and managing transmission phase discontinuity between gain modes.
Innovation Solution
A high-frequency amplifier circuit with a common-source and common-gate transistor configuration, utilizing switches and attenuators to select different resistors and capacitors for various gain modes, and incorporating a non-linearity compensation circuit to optimize S-parameters and IIP3 across gain modes, all integrated on a Silicon On Insulator (SOI) substrate for compactness and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gain mode switching is implemented in LNA, then versatility is improved, but device complexity increases due to multiple switches and attenuators
Solution Approach 1:
The LNA circuit is divided into multiple functional blocks including first and second amplification circuits, each with dedicated switching and attenuation components. This segmentation allows independent optimization of each gain mode while managing overall complexity through modular design.
Solution Approach 2:
The switching network and attenuator components serve multiple functions: they select different amplification paths, adjust gain levels, and maintain impedance matching across all gain modes. This multi-functionality reduces the need for separate components for each function.
2Adaptability or versatility
If multiple gain modes are supported, then adaptability is improved, but manufacturing precision requirements increase to meet IIP3 specifications
Solution Approach 1:
Different amplification circuits are designed with optimized local characteristics: the first amplification circuit is optimized for high gain modes while the second is optimized for low gain modes. This local optimization ensures that each circuit segment meets IIP3 requirements for its specific operating range.
Solution Approach 2:
The circuit dynamically switches between different amplification paths and adjusts attenuation levels based on the selected gain mode. This dynamic reconfiguration allows the system to maintain optimal IIP3 performance across all gain modes by activating the most suitable circuit path for each operating condition.
3Adaptability or versatility
If gain mode switching is implemented, then versatility is improved, but transmission phase discontinuity becomes more difficult to control
Solution Approach 1:
The circuit design pre-calculates and compensates for phase shifts that occur during gain mode transitions. By anticipating phase discontinuities and incorporating compensation networks in advance, the system maintains phase continuity across all gain modes without requiring real-time correction.
4Ease of manufacture
If SOI CMOS process is used instead of SiGe process, then manufacturing cost is reduced and integration is improved, but parasitic capacitance management becomes more critical
Solution Approach 1:
The design extracts and minimizes parasitic capacitance effects by carefully layout optimization of the MOS transistors, separating critical signal paths from noisy digital circuits, and using shielding techniques to reduce parasitic coupling between adjacent components on the SOI substrate.
Data Source
AI summary
High-frequency amplifier circuitry has a common-source first transistor to amplify a high-frequency input signal, a common-gate second transistor to amplify a signal amplified by the first transistor to generate an output signal, a first inductor connected between a source of the first transistor and a first reference potential node, a second inductor connected between a drain of the second transistor and a second reference potential, a first switch to select whether to connect a first attenuator on an input signal path, a second switch to select whether to connect a first resistor between the input signal path and the first reference potential node, a third switch to select at least one of second resistors connected in parallel to the second inductor, and a fourth switch to select at least one of first capacitors connected in parallel on an output signal path connected to the drain of the second transistor.