Differential Amplifier Circuit With IM2 Injection for Lower IM3

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Solution Overview

Problem

Existing amplifier circuits in modern electronic systems face challenges in reducing third-order intermodulation (IM3) distortion while maintaining common-mode rejection and performance across process and temperature variations.

Innovation Solution

The proposed amplifier circuit includes a differential pair and an intermodulation current generator with an IM2 injection circuit, which compensates for non-linearity to reduce IM3 distortion. This circuit uses current mirror circuits and a bleed current source to set quiescent and IM2 currents independently, ensuring robust performance across variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If conventional amplifier circuits are used, then the circuit structure is simple, but third-order intermodulation distortion is high

Engineering Contradiction:
ImproveIM3 distortionVSAvoidcircuit structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

An intermodulation current generator is introduced as an intermediary component that produces compensation currents specifically tailored to cancel IM3 distortion. This generator includes multiple transistors arranged in current mirror configurations that respond to input signals and generate corrective currents that are injected back into the differential pair, thereby reducing IM3 distortion without fundamentally redesigning the entire amplifier structure.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The circuit applies preliminary anti-action by generating intermodulation currents in advance that are designed to counteract the harmful IM3 distortion before it fully develops. The intermodulation current generator responds to input signals and produces compensation currents that preemptively offset the nonlinear distortion effects, reducing the net IM3 distortion in the output signal.

Inventive Principle:
Principle #9Preliminary anti-action

2Reliability

If standard amplifier designs are used, then manufacturing is straightforward, but common-mode rejection is insufficient

Engineering Contradiction:
Improvecommon-mode rejectionVSAvoidcircuit implementation
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The circuit applies local quality by configuring transistors in specific current mirror arrangements where M1 and M2 form one mirror pair while M3, M4, M5, and M6 form another. This localized asymmetric configuration around the differential pair provides targeted common-mode rejection enhancement at the critical input stage without requiring complex modifications throughout the entire circuit, maintaining manufacturability while improving reliability.

Inventive Principle:
Principle #3Local quality

3Reliability

If simple current sources are used, then the circuit is easy to implement, but performance varies with process and temperature

Engineering Contradiction:
Improveperformance stabilityVSAvoidcurrent source configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The intermodulation current generator serves multiple functions simultaneously: it generates compensation currents for IM3 distortion reduction, establishes stable quiescent current levels through its current mirror configurations, and provides temperature and process compensation. The same transistor network (M3-M6) that generates IM2 currents also functions as a stable current reference, eliminating the need for separate compensation circuits and achieving performance stability without proportional increases in complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250047246A1Amplifier circuit
Publication Date: 2025.02.06 TEXAS INSTRUMENTS INC
  • US20250047246A1 patent drawing
  • US20250047246A1 patent drawing
  • US20250047246A1 patent drawing

AI summary

An amplifier circuit includes first and second transistors, and a first current source. The first current source is coupled to first terminals of the first and second transistors. The first current source includes a second current source, and third, fourth, fifth, and sixth transistors. The third transistor has a first terminal coupled to a first terminal of the fourth transistor, and a control terminal coupled to a control terminal of the first transistor. The fourth transistor has a control terminal coupled to a control terminal of the second transistor. The fifth transistor has a first terminal coupled to a first terminal of the sixth transistor, a second terminal coupled to the second current source and to the second terminals of the third, fourth, and sixth transistors, and a control terminal coupled to a control terminal of the sixth transistor.